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1. 发明授权

US06839126B2 Photolithography process with multiple exposures 有权
标题翻译：具有多次曝光的光刻工艺
公开(公告)号：US06839126B2
公开(公告)日：2005-01-04
申请号：US10033891
申请日：2002-01-03
申请人： Yeong-Song Yen , I-Hsiung Huang , Jiunn-Ren Hwang , Kuei-Chun Hung , Ching-Hsu Chang
发明人： Yeong-Song Yen , I-Hsiung Huang , Jiunn-Ren Hwang , Kuei-Chun Hung , Ching-Hsu Chang
IPC分类号： G03F7/20 , G03B27/74 , G03B27/42 , G03B27/54
CPC分类号： G03F7/70141 , G03F7/70425 , G03F7/70466
摘要： A photolithography process with multiple exposures is provided. A photomask is placed and aligned above a wafer having a photoresist formed thereon at a predetermined distance. Multiple exposures are sequentially performed on the photoresist through the photomask. Each of the multiple exposures is provided with a respective illuminating setting that is optimized for one duty ratio of the photomask. Thereby, an optimum through-pitch performance for pattern transfer from the photomask unto the photoresist is obtained. Then, a development is performed on the photoresist.

2. 发明授权

US06391757B1 Dual damascene process 失效
标题翻译：双镶嵌工艺
公开(公告)号：US06391757B1
公开(公告)日：2002-05-21
申请号：US09875508
申请日：2001-06-06
申请人： I-Hsiung Huang , Jiunn-Ren Hwang , Yeong-Song Yen , Ching-Hsu Chang
发明人： I-Hsiung Huang , Jiunn-Ren Hwang , Yeong-Song Yen , Ching-Hsu Chang
IPC分类号： H01L2144
CPC分类号： H01L21/76835 , H01L21/76808 , H01L2221/1031
摘要： A dual damascene process involves forming a first passivation layer, a first dielectric layer and a second passivation layer on a substrate of a semiconductor wafer. A first lithography and etching process is performed to form at least one via hole in the second passivation layer and the first dielectric layer. Thereafter, a second dielectric layer and a third passivation layer are formed on the surface of the semiconductor wafer followed by performing a second lithography and etching process to form at least one trench in the third passivation layer and the second dielectric layer. The trench and the via hole together construct a dual damascene structure. Finally, a barrier layer and a metal layer are formed on the surface of the semiconductor wafer, and a chemical-mechanical-polishing (CMP) process is performed to complete the dual damascene process.
摘要翻译：双镶嵌工艺包括在半导体晶片的衬底上形成第一钝化层，第一介电层和第二钝化层。执行第一光刻和蚀刻工艺以在第二钝化层和第一介电层中形成至少一个通孔。此后，在半导体晶片的表面上形成第二电介质层和第三钝化层，随后进行第二光刻和蚀刻工艺，以在第三钝化层和第二介电层中形成至少一个沟槽。沟槽和通孔一起构成双镶嵌结构。最后，在半导体晶片的表面上形成阻挡层和金属层，进行化学机械抛光（CMP）工艺以完成双镶嵌工艺。

3. 发明授权

US06589881B2 Method of forming dual damascene structure 有权
标题翻译：形成双镶嵌结构的方法
公开(公告)号：US06589881B2
公开(公告)日：2003-07-08
申请号：US09997339
申请日：2001-11-27
申请人： I-Hsiung Huang , Jiunn-Ren Hwang , Kuei-Chun Hung , Ching-Hsu Chang
发明人： I-Hsiung Huang , Jiunn-Ren Hwang , Kuei-Chun Hung , Ching-Hsu Chang
IPC分类号： H01L21302
CPC分类号： H01L21/76835 , H01L21/76807 , H01L21/76813
摘要： A method of forming a dual damascene structure. A substrate having a conductive layer thereon is provided. A passivation layer, a first dielectric layer, an etching stop layer, a second dielectric layer and cap layer serving as a base anti-reflection coating are sequentially formed over the substrate. The cap layer and the second dielectric layer are patterned to form a first opening that exposes a portion of the etching stop layer. A patterned negative photoresist layer having a second opening therein is formed above the cap layer. The cap layer exposed by the second opening and the second dielectric layer exposed by the first opening are removed. Thereafter, the second dielectric layer exposed by the second opening is removed to form a trench and the first dielectric layer exposed by the first opening is removed to form a via opening. The passivation layer exposed by via opening and then the negative photoresist layer is removed. A conformal barrier layer and a conductive layer are sequentially formed over the trench and the via opening with the conductive layer, completely filling the trench and the via opening.
摘要翻译：形成双镶嵌结构的方法。提供其上具有导电层的基板。在衬底上顺序形成钝化层，第一介电层，蚀刻停止层，第二电介质层和用作基底防反射涂层的覆盖层。将盖层和第二介电层图案化以形成暴露蚀刻停止层的一部分的第一开口。在其上方形成了具有第二开口的图案化的负性光致抗蚀剂层。除去由第二开口暴露的盖层和由第一开口露出的第二介质层。此后，除去由第二开口露出的第二电介质层以形成沟槽，并且去除由第一开口暴露的第一电介质层以形成通孔。去除通过开口暴露的钝化层，然后去除负的光致抗蚀剂层。在沟槽和通孔开口上依次形成保形阻挡层和导电层，导电层完全填充沟槽和通孔。

4. 发明授权

US06337269B1 Method of fabricating a dual damascene structure 有权
标题翻译：制造双镶嵌结构的方法
公开(公告)号：US06337269B1
公开(公告)日：2002-01-08
申请号：US09885042
申请日：2001-06-21
申请人： I-Hsiung Huang , Jiunn-Ren Hwang , Kuei-Chun Hung
发明人： I-Hsiung Huang , Jiunn-Ren Hwang , Kuei-Chun Hung
IPC分类号： H01L214763
CPC分类号： H01L21/76811 , H01L21/76804 , H01L21/76813
摘要： The present invention fabricates a dual damascene structure. A passivation layer, a first dielectric layer, a second passivation layer, a second dielectric layer, a third passivation layer and a third dielectric layer are formed on the surface of the semiconductor wafer followed by etching the third dielectric layer to form a pattern of an upper trench of the dual damascene structure. Then the third passivation layer and the second dielectric layer are etched down to the surface of the second passivation layer so as to form a pattern of a via hole of the dual damascene structure. Thereafter, the third passivation layer and the second passivation layer not covered by the third dielectric layer and the second dielectric layer are removed. The third dielectric layer and the second passivation layer are used as hard masks to remove the second dielectric layer and the first dielectric layer until the surface of the first passivation layer. Finally, the second passivation layer and the first passivation layer not covered by the second dielectric layer and the first dielectric layer are removed to the surface of the conductive layer so completing the process of fabricating the dual damascene structure.
摘要翻译：本发明制造双镶嵌结构。在半导体晶片的表面上形成钝化层，第一介电层，第二钝化层，第二介电层，第三钝化层和第三介电层，然后蚀刻第三介电层，形成图案双层镶嵌结构的上沟槽。然后，将第三钝化层和第二介电层向下蚀刻到第二钝化层的表面，以形成双镶嵌结构的通孔的图案。此后，除去未被第三电介质层和第二电介质层覆盖的第三钝化层和第二钝化层。第三介电层和第二钝化层用作硬掩模以去除第二介电层和第一介电层直到第一钝化层的表面。最后，将第二钝化层和未被第二介电层和第一介电层覆盖的第一钝化层除去到导电层的表面，从而完成制造双镶嵌结构的工艺。

5. 发明授权

US06680163B2 Method of forming opening in wafer layer 有权
标题翻译：在晶片层中形成开口的方法
公开(公告)号：US06680163B2
公开(公告)日：2004-01-20
申请号：US10328769
申请日：2002-12-23
申请人： Jiunn-Ren Hwang , I-Hsiung Huang
发明人： Jiunn-Ren Hwang , I-Hsiung Huang
IPC分类号： G03C556
CPC分类号： G03F7/0035 , G03F7/40
摘要： A method of forming an opening in a wafer layer is described. At least two patterned photoresist layers are formed on a wafer layer. Each photoresist layer comprises patterns of various configurations. The photoresist layers are stacked to form an opening pattern that expose the underlying wafer layer by superpositioning the space between the patterns in the first photoresist layer and the space between the patterns in the second photoresist layer. The wafer layer exposed by the opening pattern is then etched to form an opening.
摘要翻译：描述了在晶片层中形成开口的方法。至少两个图案化的光致抗蚀剂层形成在晶片层上。每个光致抗蚀剂层包括各种配置的图案。层叠光致抗蚀剂层以形成通过叠加第一光致抗蚀剂层中的图案之间的空间和第二光致抗蚀剂层中的图案之间的空间来暴露下面的晶片层的开口图案。然后蚀刻由开口图案曝光的晶片层以形成开口。

6. 发明授权

US06656667B2 Multiple resist layer photolithographic process 失效
公开(公告)号：US06656667B2
公开(公告)日：2003-12-02
申请号：US09835013
申请日：2001-04-13
申请人： I-Hsiung Huang , Jiunn-Ren Hwang
发明人： I-Hsiung Huang , Jiunn-Ren Hwang
IPC分类号： G03F700
CPC分类号： G03F7/0035
摘要： A multiple resist layer photolithographic process. A substrate having an insulation layer and a first photoresist layer sequentially stacked thereon is provided. A first light-exposure is conducted to transfer a pattern on a photomask to the first photoresist layer, thereby forming a first exposure pattern. A post-exposure baking is carried out and then the first photoresist layer is developed. A second photoresist layer is formed over the patterned first photoresist layer. A second photo-exposure is conducted to transfer the pattern on the same photomask to the second photoresist layer, thereby forming a second exposure pattern. The second exposure pattern and the first exposure pattern are aligned. Finally, the second photoresist layer is developed.

7. 发明授权

US06579790B1 Dual damascene manufacturing process 失效
标题翻译：双镶嵌制造工艺
公开(公告)号：US06579790B1
公开(公告)日：2003-06-17
申请号：US09707314
申请日：2000-11-06
申请人： I-Hsiung Huang , Jiunn-Ren Hwang
发明人： I-Hsiung Huang , Jiunn-Ren Hwang
IPC分类号： H01L214763
CPC分类号： H01L21/76811 , H01L21/0274
摘要： A method of fabricating a dual damascene opening in a dielectric layer above a substrate. A first photoresist layer having a first opening therein is formed over the dielectric layer. The first opening exposes the dielectric layer at a position where a via is desired. A buffer layer is formed over the first photoresist layer. A second photoresist layer having a second opening is formed over the buffer layer. The second opening exposes the area where a conductive wire is desired. The first opening and the second opening together form a metallic interconnect structure. Using the first and the second photoresist layer as a mask, a dual damascene structural opening that includes a via opening and a conductive wire trench is formed in the dielectric layer.
摘要翻译：在衬底上方的电介质层中制造双镶嵌开口的方法。在电介质层上方形成有第一开口的第一光致抗蚀剂层。第一开口将电介质层暴露在期望通孔的位置处。在第一光致抗蚀剂层上形成缓冲层。在缓冲层上形成具有第二开口的第二光致抗蚀剂层。第二个开口露出需要导线的区域。第一开口和第二开口一起形成金属互连结构。使用第一和第二光致抗蚀剂层作为掩模，在电介质层中形成包括通孔开口和导线沟槽的双镶嵌结构开口。

8. 发明授权

US06541782B2 Electron beam photolithographic process 有权
公开(公告)号：US06541782B2
公开(公告)日：2003-04-01
申请号：US09734240
申请日：2000-12-05
申请人： I-Hsiung Huang , Jiunn-Ren Hwang
发明人： I-Hsiung Huang , Jiunn-Ren Hwang
IPC分类号： H01L2100
CPC分类号： G03F7/2037 , H01J2237/0044 , H01J2237/3175 , H01J2237/31796
摘要： An electron beam photolithographic process for patterning an insulation layer over a substrate. A conductive photoresist layer having a conjugate structure is formed over the insulation layer. An electron beam photolithographic process is conducted using a photomask so that the pattern on the photomask is transferred to the conductive photoresist layer.

9. 发明授权

US06312855B1 Three-phase phase shift mask 有权
标题翻译：三相相移掩模
公开(公告)号：US06312855B1
公开(公告)日：2001-11-06
申请号：US09444466
申请日：1999-11-22
申请人： Jiunn-Ren Hwang , I-Hsiung Huang , Anseime Chen
发明人： Jiunn-Ren Hwang , I-Hsiung Huang , Anseime Chen
IPC分类号： G03F900
CPC分类号： G03F1/28
摘要： A three-phase phase shift mask. On a transparent substrate, a non-transparent pattern covering a portion of the transparent substrate is formed, while the other portion of the substrate is remained exposed. A proximity region around a comer of the non-transparent pattern is equally partitioned three phase-shift areas different from each other with a phase shift of 120°. The formation of these three phase-shift areas uses two etching steps to form a first and a second phase-shift areas, while a portion of the exposed substrate is etched twice as a third phase-shift area.
摘要翻译：三相相移掩模。在透明基板上，形成覆盖透明基板的一部分的不透明图案，同时基板的另一部分保持露出。不透明图案的周围的邻近区域被相等地划分为相位相差120°的三个相移区域。这三个相移区域的形成使用两个蚀刻步骤来形成第一和第二相移区域，而暴露的衬底的一部分被蚀刻两次作为第三相移区域。

10. 发明授权

US06664028B2 Method of forming opening in wafer layer 失效
公开(公告)号：US06664028B2
公开(公告)日：2003-12-16
申请号：US09729575
申请日：2000-12-04
申请人： Jiunn-Ren Hwang , I-Hsiung Huang
发明人： Jiunn-Ren Hwang , I-Hsiung Huang
IPC分类号： G03C556
CPC分类号： G03F7/0035 , G03F7/40
摘要： A method of forming an opening in a wafer layer. At least two patterned photoresist layers are formed on a wafer layer. Using different photoresist layers, many openings are defined. The wafer layer is then etched to form the opening. Each photoresist layer has a parallel linear pattern such as parallel strips or an array of rectangular blocks. The photoresist layers are superposed in a way that spaces between the patterns for each photoresist layers overlapped with each other for form openings that expose the underlying wafer layers. The wafer layer exposed in the openings is then etched to form contact/via holes without rounded corners while the rounded profiles has been cancelled by the superposition of the photoresist layers.

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