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1. 发明申请

US20070033302A1 Virtual first in first out direct memory access device 有权
标题翻译：虚拟先进先出直接内存访问设备
公开(公告)号：US20070033302A1
公开(公告)日：2007-02-08
申请号：US11495888
申请日：2006-07-31
申请人： Yen-Yu Lin , Shih-Chang Hu , Shiau-Wan Chen
发明人： Yen-Yu Lin , Shih-Chang Hu , Shiau-Wan Chen
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO unit is provided. In the virtual FIFO DMA device, a DMA unit is for transferring data between the UART unit and the virtual FIFO unit. A virtual FIFO controller, which has a read pointer and a write pointer, is electrically connected with the DMA unit. When the DMA unit reads data from or writes data into the virtual FIFO unit, the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer. A virtual port is electrically connected to the DMA unit and the processor. A processor reads data from or writes data into the virtual FIFO unit via the virtual port and the DMA unit.
摘要翻译：提供了一种应用于具有处理器，UART单元和虚拟FIFO单元的电子设备中的先进先出（FIFO）直接存储器访问（DMA）设备。在虚拟FIFO DMA设备中，DMA单元用于在UART单元和虚拟FIFO单元之间传输数据。具有读指针和写指针的虚拟FIFO控制器与DMA单元电连接。当DMA单元从虚拟FIFO单元读取数据或将数据写入虚拟FIFO单元时，虚拟FIFO控制器相应地改变读指针或写指针的值。虚拟端口电连接到DMA单元和处理器。处理器通过虚拟端口和DMA单元从数据读取数据或将数据写入虚拟FIFO单元。

2. 发明授权

US07698474B2 Virtual first in first out (FIFO) direct memory access (DMA) device, electronic device and memory access method using the same 有权
标题翻译：虚拟先进先出（FIFO）直接存储器访问（DMA）器件，电子设备和存储器访问方法使用相同
公开(公告)号：US07698474B2
公开(公告)日：2010-04-13
申请号：US11495888
申请日：2006-07-31
申请人： Yen-Yu Lin , Shih-Chang Hu , Shiau-Wan Chen
发明人： Yen-Yu Lin , Shih-Chang Hu , Shiau-Wan Chen
IPC分类号： G06F13/28 , G06F5/00
CPC分类号： G06F13/28
摘要： A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO unit is provided. In the virtual FIFO DMA device, a DMA unit is for transferring data between the UART unit and the virtual FIFO unit. A virtual FIFO controller, which has a read pointer and a write pointer, is electrically connected with the DMA unit. When the DMA unit reads data from or writes data into the virtual FIFO unit, the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer. A virtual port is electrically connected to the DMA unit and the processor. A processor reads data from or writes data into the virtual FIFO unit via the virtual port and the DMA unit.
摘要翻译：提供了一种应用于具有处理器，UART单元和虚拟FIFO单元的电子设备中的先进先出（FIFO）直接存储器访问（DMA）设备。在虚拟FIFO DMA设备中，DMA单元用于在UART单元和虚拟FIFO单元之间传输数据。具有读指针和写指针的虚拟FIFO控制器与DMA单元电连接。当DMA单元从虚拟FIFO单元读取数据或将数据写入虚拟FIFO单元时，虚拟FIFO控制器相应地改变读指针或写指针的值。虚拟端口电连接到DMA单元和处理器。处理器通过虚拟端口和DMA单元从数据读取数据或将数据写入虚拟FIFO单元。

3. 发明申请

US20050125571A1 Virtual first in first out direct memory access device 审中-公开
标题翻译：虚拟先进先出直接内存访问设备
公开(公告)号：US20050125571A1
公开(公告)日：2005-06-09
申请号：US11002391
申请日：2004-12-03
申请人： Yen-Yu Lin , Shih-Chang Hu , Shiau-Wan Chen
发明人： Yen-Yu Lin , Shih-Chang Hu , Shiau-Wan Chen
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO is provided. In the virtual FIFO DMA device, a DMA unit is for transferring data between the UART unit and the virtual FIFO. A virtual FIFO controller, which has a read pointer and a write pointer, is electrically connected with the DMA unit. When the DMA unit reads data from or saves data into the virtual FIFO, the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer. A virtual port is electrically connected with the DMA unit and the processor respectively. A processor reads data from or writes data into the virtual FIFO via the virtual port and the DMA unit.
摘要翻译：提供了一种应用于具有处理器，UART单元和虚拟FIFO的电子设备中的虚拟先进先出（FIFO）直接存储器访问（DMA）设备。在虚拟FIFO DMA设备中，DMA单元用于在UART单元和虚拟FIFO之间传输数据。具有读指针和写指针的虚拟FIFO控制器与DMA单元电连接。当DMA单元从虚拟FIFO读取数据或将数据保存到虚拟FIFO中时，虚拟FIFO控制器相应地改变读指针或写指针的值。虚拟端口分别与DMA单元和处理器电连接。处理器通过虚拟端口和DMA单元从数据读取数据或将数据写入虚拟FIFO。

4. 发明申请

US20080201528A1 MEMORY ACCESS SYSTEMS FOR CONFIGURING WAYS AS CACHE OR DIRECTLY ADDRESSABLE MEMORY 审中-公开
标题翻译：用于配置方式的存储器访问系统作为缓存或直接寻址的存储器
公开(公告)号：US20080201528A1
公开(公告)日：2008-08-21
申请号：US12107965
申请日：2008-04-23
申请人： Ting-Cheng Hsu , Yen-Yu Lin , Shien-Tai Pan
发明人： Ting-Cheng Hsu , Yen-Yu Lin , Shien-Tai Pan
IPC分类号： G06F12/00
CPC分类号： G06F12/0653 , G06F12/0895 , Y02D10/13
摘要： A memory system is provided. A processor provides a data access address. A memory device includes a predetermined number of ways. The processor selectively configures a selected number less than or equal to the predetermined number of the ways as cache memory belonging to a cacheable region, and configures remaining ways as directly addressable memory belonging to a directly addressable region by memory configuration information. A memory controller determines the data access address corresponding to the cacheable region or the directly addressable region, selects only the way in the directly addressable region corresponding to the data access address when the data access address corresponds to the directly addressable region, and selects only the way(s) belonging to the cacheable region when the data access address corresponds to the cacheable region. A configuration controller monitors the status of the ways and adjusting the memory configuration information according to the status of the ways.
摘要翻译：提供了一种存储系统。处理器提供数据访问地址。存储器装置包括预定数量的方式。处理器有选择地将属于可高速缓存区域的高速缓冲存储器的预定数目的小于或等于预定数量的选择性配置，并且通过存储器配置信息将属于可直接寻址区域的直接可寻址存储器的剩余方式配置。存储器控制器确定与可高速缓存区域或直接可寻址区域相对应的数据访问地址，当数据访问地址对应于直接可寻址区域时，仅选择对应于数据访问地址的直接可寻址区域中的方式，并且仅选择当数据访问地址对应于可缓存区域时属于可缓存区域的方式。配置控制器根据方式的状态监控方式的状态并调整内存配置信息。

5. 发明申请

US20070153093A1 Apparatus and method for image capturing with an image scaling unit to scale a portion of an image 审中-公开
标题翻译：用于利用图像缩放单元进行图像捕获以缩放图像的一部分的装置和方法
公开(公告)号：US20070153093A1
公开(公告)日：2007-07-05
申请号：US11322499
申请日：2005-12-30
申请人： Yen-Yu Lin , Tien-Yu Chang
发明人： Yen-Yu Lin , Tien-Yu Chang
IPC分类号： H04N5/228
CPC分类号： H04N5/2628 , H04N5/23296
摘要： An apparatus for image capturing includes a sensing device, an image processing unit, an image scaling unit, and a memory device. The sensing device is for capturing an image, and the image processing unit is for processing the image. The memory device is for storing the portion of the image, and the image scaling unit is for scaling the portion of the image. After the image processing unit processes the image, only the portion of the image is stored in the memory device to be transmitted to the image scaling unit for image scaling.
摘要翻译：一种用于图像捕获的装置包括感测装置，图像处理单元，图像缩放单元和存储装置。感测装置用于拍摄图像，图像处理单元用于处理图像。存储装置用于存储图像的一部分，图像缩放单元用于缩放图像的一部分。在图像处理单元处理图像之后，仅将图像的一部分存储在存储器件中以被发送到用于图像缩放的图像缩放单元。

6. 发明申请

US20070050553A1 PROCESSING MODULES WITH MULTILEVEL CACHE ARCHITECTURE 有权
标题翻译：具有多个高速缓存架构的处理模块
公开(公告)号：US20070050553A1
公开(公告)日：2007-03-01
申请号：US11307073
申请日：2006-01-23
申请人： Ting-Cheng Hsu , Yen-Yu Lin , Chih-Wei Ko , Chang-Fu Lin
发明人： Ting-Cheng Hsu , Yen-Yu Lin , Chih-Wei Ko , Chang-Fu Lin
IPC分类号： G06F12/00
CPC分类号： G06F12/0848 , G06F12/0857 , G06F12/0897
摘要： A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.
摘要翻译：具有多级缓存架构的处理模块，包括：处理器; 耦合到所述处理器的用于高速缓存用于所述处理器的数据的一级缓存（L 1），其中所述L 1高速缓存具有至少一个L 1可缓存范围; 耦合到所述L1缓存的二级（L2）高速缓存，用于缓存用于所述处理器的数据，其中所述L 2高速缓存具有至少一个L 2可缓存范围，并且所述L 1可缓存范围和所述L 2可缓存范围是相互排斥的以及耦合到L 1缓存和L 2高速缓存的存储器接口，用于在L 1高速缓存和存储器之间传送数据，并用于在L 2高速缓存和存储器之间传送数据。

7. 发明授权

US07262644B2 Method and apparatus for switching frequency of a system clock 有权
标题翻译：用于切换系统时钟频率的方法和装置
公开(公告)号：US07262644B2
公开(公告)日：2007-08-28
申请号：US11163676
申请日：2005-10-26
申请人： Yen-Yu Lin
发明人： Yen-Yu Lin
IPC分类号： H03B19/00
CPC分类号： H03K23/667
摘要： A system clock switching apparatus, which includes a clock source for providing a reference clock signal; a frequency divider electrically connected to the clock source for dividing the reference clock signal to produce a frequency-divided signal and a system clock signal; and an enable signal generator electrically connected to the frequency divider for dividing the frequency-divided signal to produce at least one enable signal. The frequency divider switches the frequency of the system clock signal at a time period corresponding to a pulse edge of the frequency-divided signal.
摘要翻译：一种系统时钟切换装置，包括用于提供参考时钟信号的时钟源; 电连接到时钟源的分频器，用于划分参考时钟信号以产生分频信号和系统时钟信号; 电连接到分频器的使能信号发生器，用于分频分频信号以产生至少一个使能信号。分频器在与分频信号的脉冲沿相对应的时间段切换系统时钟信号的频率。

8. 发明申请

US20070153117A1 Apparatus and method for adjusting display-related setting of an electronic device 审中-公开
标题翻译：用于调整电子设备的显示相关设置的装置和方法
公开(公告)号：US20070153117A1
公开(公告)日：2007-07-05
申请号：US11320656
申请日：2005-12-30
申请人： Yen-Yu Lin , Chang-Jung Kao , Shu-Wen Teng
发明人： Yen-Yu Lin , Chang-Jung Kao , Shu-Wen Teng
IPC分类号： H04N5/235 , G03B7/00
CPC分类号： G03B7/093 , G09G3/3406 , G09G2320/064 , G09G2320/0673 , G09G2360/145 , H04N5/202 , H04N5/23293 , H04N5/2353 , H04N5/58 , H04N21/41407 , H04N21/4223 , H04N21/4318 , H04N21/44008
摘要： An apparatus and method for adjusting display-related setting of an electronic device are disclosed. The apparatus includes an image sensing device, an image signal processing unit, and a determination device. The image sensing device is for capturing a number of images according to a number of exposure time values and outputting image signals accordingly. The image signal processing unit is coupled to the image sensing device for processing the image signals and outputting a number of image luminance values accordingly. The processor is coupled to the image signal processing unit for adjusting the display-related setting of the electronic device according to the image luminance values and exposure time values.
摘要翻译：公开了一种用于调整电子设备的显示相关设置的装置和方法。该装置包括图像感测装置，图像信号处理单元和确定装置。图像感测装置用于根据多个曝光时间值捕获多个图像并相应地输出图像信号。图像信号处理单元耦合到图像感测装置，用于处理图像信号并相应地输出多个图像亮度值。处理器耦合到图像信号处理单元，用于根据图像亮度值和曝光时间值调整电子设备的显示相关设置。

9. 发明申请

US20060091918A1 METHOD AND APPARATUS FOR SWITCHING FREQUENCY OF A SYSTEM CLOCK 有权
标题翻译：用于切换系统时钟频率的方法和装置
公开(公告)号：US20060091918A1
公开(公告)日：2006-05-04
申请号：US11163676
申请日：2005-10-26
申请人： Yen-Yu Lin
发明人： Yen-Yu Lin
IPC分类号： H03B19/00
CPC分类号： H03K23/667
摘要： A system clock switching apparatus, which includes a clock source for providing a reference clock signal; a frequency divider electrically connected to the clock source for dividing the reference clock signal to produce a frequency-divided signal and a system clock signal; and an enable signal generator electrically connected to the frequency divider for dividing the frequency-divided signal to produce at least one enable signal. The frequency divider switches the frequency of the system clock signal at a time period corresponding to a pulse edge of the frequency-divided signal.
摘要翻译：一种系统时钟切换装置，包括用于提供参考时钟信号的时钟源; 电连接到时钟源的分频器，用于划分参考时钟信号以产生分频信号和系统时钟信号; 电连接到分频器的使能信号发生器，用于分频分频信号以产生至少一个使能信号。分频器在与分频信号的脉冲沿相对应的时间段切换系统时钟信号的频率。

10. 发明授权

US07596661B2 Processing modules with multilevel cache architecture 有权
标题翻译：处理具有多级缓存架构的模块
公开(公告)号：US07596661B2
公开(公告)日：2009-09-29
申请号：US11307073
申请日：2006-01-23
申请人： Ting-Cheng Hsu , Yen-Yu Lin , Chih-Wei Ko , Chang-Fu Lin
发明人： Ting-Cheng Hsu , Yen-Yu Lin , Chih-Wei Ko , Chang-Fu Lin
IPC分类号： G06F13/00
CPC分类号： G06F12/0848 , G06F12/0857 , G06F12/0897
摘要： A processing module with multilevel cache architecture, including: a processor; a level-one (L1) cache, coupled to the processor, for caching data for the processor, wherein the L1 cache has at least one L1 cacheable range; a level-two (L2) cache, coupled to the L1 cache, for caching data for the processor, wherein the L2 cache has at least one L2 cacheable range, and the L1 cacheable range and the L2 cacheable range are mutually exclusive; and a memory interface, coupled to the L1 cache and the L2 cache, for transferring data between the L1 cache and a memory and for transferring data between the L2 cache and the memory.
摘要翻译：具有多级缓存架构的处理模块，包括：处理器; 耦合到所述处理器的用于缓存所述处理器的数据的一级（L1）高速缓存，其中所述L1高速缓存具有至少一个L1可高速缓存的范围; 耦合到L1高速缓存用于缓存处理器的数据的二级（L2）高速缓存，其中所述L2高速缓存具有至少一个L2可高速缓存的范围，并且所述L1高速缓存范围和所述L2高速缓存范围是相互排斥的; 以及耦合到L1高速缓存和L2高速缓存的存储器接口，用于在L1高速缓存和存储器之间传送数据并用于在L2高速缓存和存储器之间传送数据。

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