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    • 2. 发明授权
    • Substrate biasing circuit and semiconductor integrated circuit device
    • 基板偏置电路和半导体集成电路器件
    • US6075404A
    • 2000-06-13
    • US56748
    • 1998-04-08
    • Yasuyuki ShindohHirofumi Watanabe
    • Yasuyuki ShindohHirofumi Watanabe
    • G11C11/413G05F3/20G11C11/408H01L21/822H01L27/04H02M3/07H03K19/094G05F3/02
    • G05F3/205
    • A substrate biasing circuit includes a logical threshold potential output circuit including transistors formed on a semiconductor substrate and generating a logical threshold potential. A potential compare control circuit compares the logical threshold potential with a reference potential and generating a control potential based on a comparison result. A substrate bias generating circuit generates, as long as the control potential indicates that the logical threshold potential is not equal to the reference potential, a substrate potential applied to the semiconductor substrate so that the logical threshold potential is equal to the reference potential, and stops operating after the logical threshold potential becomes equal to the reference potential. A switch circuit breaks a pass-through current path formed in the logical threshold potential output circuit when the control potential indicates that the logical threshold potential becomes equal to the reference potential.
    • 衬底偏置电路包括逻辑阈值电位输出电路,其包括形成在半导体衬底上并产生逻辑阈值电位的晶体管。 潜在的比较控制电路将逻辑阈值电位与参考电位进行比较,并且基于比较结果产生控制电位。 衬底偏置产生电路只要控制电位指示逻辑阈值电位不等于参考电位就产生施加到半导体衬底的衬底电位,使得逻辑阈值电位等于参考电位,并且停止 在逻辑阈值电位变得等于参考电位之后运行。 当控制电位指示逻辑阈值电位变得等于参考电位时,开关电路断开形成在逻辑阈值电位输出电路中的通过电流路径。
    • 9. 发明申请
    • SEMICONDUCTOR DEVICE AND IMAGING APPARATUS
    • 半导体器件和成像装置
    • US20130234277A1
    • 2013-09-12
    • US13793445
    • 2013-03-11
    • Takaaki NegoroHirofumi WatanabeYutaka HayashiToshitaka OtaYasushi Nagamune
    • Takaaki NegoroHirofumi WatanabeYutaka HayashiToshitaka OtaYasushi Nagamune
    • H01L27/146H01L29/73
    • H01L27/14681H01L27/14683H01L29/73H01L29/739H01L31/1105
    • The invention relates to a semiconductor device having a vertical transistor bipolar structure of emitter, base, and collector formed in this order from a semiconductor substrate surface in a depth direction. The semiconductor device includes an electrode embedded from the semiconductor substrate surface into the inside and insulated by an oxide film. In the surface of the substrate, a first-conductivity-type first semiconductor region, a second-conductivity-type second semiconductor region, and a first-conductivity-type third semiconductor region are arranged, from the surface side, inside a semiconductor device region surrounded by the electrode and along the electrode with the oxide film interposed therebetween, the second semiconductor region located below the first semiconductor region, the third semiconductor region located below the second semiconductor region. The electrode is insulated from the first to third semiconductor regions, and current gain is variable through application of voltage to the electrode.
    • 本发明涉及一种半导体器件,其具有从半导体衬底表面沿深度方向依次形成的发射极,基极和集电极的垂直晶体管双极结构。 半导体器件包括从半导体衬底表面嵌入内部并由氧化物膜绝缘的电极。 在基板的表面中,从第一导电型第一半导体区域,第二导电型第二半导体区域和第一导电型第三半导体区域的表面侧配置在半导体器件区域 被电极围绕并且沿着电极,氧化膜插入其间,位于第一半导体区域下方的第二半导体区域,位于第二半导体区域下方的第三半导体区域。 电极与第一至第三半导体区域绝缘​​,电流增益可通过向电极施加电压而变化。