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1. 发明授权

US5530144A Process for producing a phosphorus-vanadium oxide catalyst precursor, process for producing a phosphorus-vanadium oxide catalyst, and process for producing maleic anhydride by vapor phase oxidation using the catalyst 失效
标题翻译：磷钒氧化物催化剂前体的制造方法，磷 - 钒氧化物催化剂的制造方法，使用该催化剂的气相氧化法制造马来酸酐的方法
公开(公告)号：US5530144A
公开(公告)日：1996-06-25
申请号：US359596
申请日：1994-12-20
申请人： Yasushi Tsurita , Masayoshi Murayama , Kenji Shima , Masumi Ito
发明人： Yasushi Tsurita , Masayoshi Murayama , Kenji Shima , Masumi Ito
IPC分类号： B01J27/198 , C01B25/08 , C07C51/215 , C07D307/34 , C01B15/16 , C07D307/36
CPC分类号： C07C51/215 , B01J23/002 , B01J27/198 , C01B25/08 , B01J2523/00
摘要： A process for producing a precursor of a phosphorus-vanadium oxide catalyst for production of maleic anhydride by vapor phase oxidation of a hydrocarbon having 4 carbon atoms, which comprises reacting phosphoric acid and a pentavalent vanadium compound in an organic solvent capable of reducing at least a portion of the pentavalent vanadium to a valence state of +4, the phosphoric acid being substantially composed of orthophosphoric acid, and a phosphoric acid solution whose concentration is 88 to 96% being used as a source of the phosphoric acid; and a process for producing the catalyst comprising dry-pulverizing the catalyst precursor.
摘要翻译：一种用于通过气相氧化具有4个碳原子的烃来生产马来酸酐的磷 - 钒氧化物催化剂的前体的方法，该方法包括使磷酸和五价钒化合物在至少能够还原至少一种五价钒的一部分为+4的价态，磷酸基本上由正磷酸组成，浓度为88〜96％的磷酸溶液用作磷酸源; 以及一种生产该催化剂的方法，包括将该催化剂前体干粉碎。

2. 发明授权

US5591870A Process for producing a vanadium-phosphorus oxide catalyst precursor 失效
标题翻译：钒 - 磷氧化物催化剂前体的制备方法
公开(公告)号：US5591870A
公开(公告)日：1997-01-07
申请号：US480916
申请日：1995-06-07
申请人： Masakatsu Hatano , Masayoshi Murayama , Kenji Shima , Masumi Ito
发明人： Masakatsu Hatano , Masayoshi Murayama , Kenji Shima , Masumi Ito
IPC分类号： B01J23/22 , B01J27/198 , C07C51/215 , C07C57/05
CPC分类号： C07C51/215 , B01J23/002 , B01J23/22 , B01J27/198 , B01J2523/00
摘要： A process for producing a vanadium-phosphorus oxide-containing catalyst precursor, which comprises (a) introducing into an organic solvent a vanadium alkoxide as a pentavalent vanadium compound and a phosphorus compound in the presence of a reducing agent capable of reducing the pentavalent vanadium compound to a tetravalent state, (b) hydrolyzing at least a part of the vanadium alkoxide before or after the introduction of the phosphorus compound, and (c) heating the vanadium-containing liquid medium obtained in step (b), in the presence of the phosphorus compound to reduce at least a part of vanadium to a tetravalent state.
摘要翻译：一种含钒 - 氧化磷的催化剂前体的制备方法，其包括（a）在能够还原五价钒化合物的还原剂的存在下将有机溶剂中的钒醇盐作为五价钒化合物和磷化合物引入（b）在引入磷化合物之前或之后水解至少一部分钒醇盐，和（c）在步骤（b）中获得的含钒液体介质中，在磷化合物以将至少一部分钒还原成四价态。

3. 发明授权

US5496787A Process for producing a vanadium-phosphorus oxide catalyst precursor 失效
标题翻译：钒 - 磷氧化物催化剂前体的制备方法
公开(公告)号：US5496787A
公开(公告)日：1996-03-05
申请号：US187715
申请日：1994-01-28
申请人： Masakatsu Hatano , Masayoshi Murayama , Kenji Shima , Masumi Ito
发明人： Masakatsu Hatano , Masayoshi Murayama , Kenji Shima , Masumi Ito
IPC分类号： B01J23/22 , B01J27/198 , C07C51/215 , C07C57/05
CPC分类号： C07C51/215 , B01J23/002 , B01J23/22 , B01J27/198 , B01J2523/00
摘要： A process for producing a vanadium-phosphorus oxide-containing catalyst precursor, which comprises (a) introducing into an organic solvent a vanadium alkoxide as a pentavalent vanadium compound and a phosphorus compound in the presence of a reducing agent capable of reducing the pentavalent vanadium compound to a tetravalent state, (b) hydrolyzing at least a part of the vanadium alkoxide before or after the introduction of the phosphorus compound, and (c) heating the vanadium-containing liquid medium obtained in step (b), in the presence of the phosphorus compound to reduce at least a part of vanadium to a tetravalent state.
摘要翻译：一种含钒 - 氧化磷的催化剂前体的制备方法，其包括（a）在能够还原五价钒化合物的还原剂的存在下将有机溶剂中的钒醇盐作为五价钒化合物和磷化合物引入（b）在引入磷化合物之前或之后水解至少一部分钒醇盐，和（c）在步骤（b）中获得的含钒液体介质中，在磷化合物以将至少一部分钒还原成四价态。

4. 发明授权

US5021384A Process for producing crystalline oxide of vanadium-phosphorus system and catalyst containing the crystalline oxide 失效
标题翻译：制备钒 - 磷体系的结晶氧化物的方法和含有结晶氧化物的催化剂
公开(公告)号：US5021384A
公开(公告)日：1991-06-04
申请号：US414313
申请日：1989-09-29
申请人： Masakatsu Hatano , Masayoshi Murayama , Kenji Shima , Masumi Ito
发明人： Masakatsu Hatano , Masayoshi Murayama , Kenji Shima , Masumi Ito
IPC分类号： B01J27/198 , C01B25/37 , C01B25/45 , C07C51/215 , C07C51/25 , C07C51/54 , C07D307/60
CPC分类号： C07C51/25 , B01J27/198 , C07C51/215 , C07C51/252
摘要： A process for producing a crystalline oxide of vanadium-phosphorus system, which comprises hydrothermally treating an aqueous medium containing (1) a tetravalent vanadium compound, (2) a pentavalent phosphorus compound, (3) a coordinate compound having at least two ligand atoms selected from the group consisting of oxygen atoms and nitrogen atoms and (4) a compound of at least one metal element selected from the group consisting of iron, nickel, cobalt and chromium, to form a crystalline oxide of vanadium-phosphorus system having an X-ray diffraction pattern shown in Table A: TABLE A ______________________________________ X-ray diffraction peaks (Anticathode: Cu-K.alpha.) 2.theta. (.+-. 0.2.degree.) ______________________________________ 15.6.degree. 19.7.degree. 24.3.degree. 27.2.degree. 28.8.degree. 30.5.degree. 33.8.degree. ______________________________________

5. 发明授权

US5128299A Process for producing crystalline oxide of vanadium-phosphorus system 失效
标题翻译：生产钒 - 磷系结晶氧化物的工艺
公开(公告)号：US5128299A
公开(公告)日：1992-07-07
申请号：US623091
申请日：1990-12-06
申请人： Masakatsu Hatano , Masayoshi Murayama , Kenji Shima , Masumi Ito
发明人： Masakatsu Hatano , Masayoshi Murayama , Kenji Shima , Masumi Ito
IPC分类号： B01J27/198 , C01B25/37 , C01B25/45 , C07C51/215 , C07C51/25 , C07C51/54 , C07D307/60
CPC分类号： C07C51/25 , B01J27/198 , C07C51/215 , C07C51/252
摘要： A process for producing a crystalline oxide of vanadium-phosphorus system, which comprises hydrothermally treating an aqueous medium containing (1) a tetravalent vanadium compound, (2) a pentavalent phosphorus compound, (3) a coordinate compound having at least two ligand atoms selected from the group consisting of oxygen atoms and nitrogen atoms and (4) a compound of at least one metal element selected from the group consisting of iron, nickel, cobalt and chromium, to form a crystalline oxide of vanadium-phosphorus system having an X-ray diffraction pattern shown in Table A: TABLE A ______________________________________ X-ray diffraction peaks (Anticathode: Cu--K.alpha.) 2.theta. (.+-.0.2.degree.) ______________________________________ 15.6.degree. 19.7.degree. 24.3.degree. 27.2.degree. 28.8.degree. 30.5.degree. 33.8.degree. ______________________________________
摘要翻译：一种制备钒 - 磷体系的结晶氧化物的方法，其包括水热处理含有（1）四价钒化合物的水性介质，（2）五价磷化合物，（3）选择至少两个配体原子的配位化合物由氧原子和氮原子组成的组和（4）选自铁，镍，钴和铬中的至少一种金属元素的化合物，形成具有X射线衍射的钒 - 磷系的结晶氧化物， X-射线衍射峰 - （Antichodhode：Cu-Kα）-2°（+/- 0.2°）-15.6°19.7°24.3°-27.2°28.8°30.5°33.8° -

6. 发明授权

US08380897B2 Host computer, computer terminal, and card access method 失效
标题翻译：主机，计算机终端和卡访问方式
公开(公告)号：US08380897B2
公开(公告)日：2013-02-19
申请号：US13486661
申请日：2012-06-01
申请人： Masayoshi Murayama
发明人： Masayoshi Murayama
IPC分类号： G06F3/00
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit that includes both a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information for an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.
摘要翻译：根据一个实施例，主机控制器包括：传输电路，根据串行传输格式，根据串行传输格式对接收数据进行解码的接收电路，产生卡时钟的可变频率时钟发生器，以及传送时钟，将卡时钟输出到存储卡的卡时钟输出单元，包括传输接口的接口单元，传输接口与传送时钟同步地将传输数据从传输电路传送到存储卡，接收接口，其将接收到的数据从存储卡传送到与传送时钟同步的接收电路;以及设置寄存器电路，其保存用于存储卡的输入/输出方法的设置信息，并且控制由存储卡生成的传送时钟的频率可变频时钟发生器，根据设定信息。

7. 发明申请

US20120054531A1 HOST CONTROLLER, SEMICONDUCTOR DEVICE AND METHOD FOR SETTING SAMPLING PHASE 失效
标题翻译：主机控制器，半导体器件和设置采样相位的方法
公开(公告)号：US20120054531A1
公开(公告)日：2012-03-01
申请号：US13075309
申请日：2011-03-30
申请人： Masayoshi Murayama
发明人： Masayoshi Murayama
IPC分类号： G06F1/04
CPC分类号： H03L7/081 , G06F2213/0038
摘要： According to one embodiment, there is provided a host controller, which samples reception data in a VDS mode and an FDS mode, includes a VDS phase register which holds a phase shift amount in the VDS mode, an FDS phase register which holds a phase shift amount in the FDS mode, a mode setting unit configured to indicate in which of the VDS mode and the FDS mode data is sampled, a sampling position setting unit which selects the phase shift amount set in one of the VDS and the FDS phase register in accordance with a setting value of the mode setting unit, and provides the selected phase shift amount as a sampling position, and a clock phase shift unit which shifts a phase of an input clock signal in accordance with the shift amount, and provides the shifted input clock signal as a sampling clock.
摘要翻译：根据一个实施例，提供了以VDS模式和FDS模式对接收数据进行采样的主机控制器，包括保持VDS模式中的相移量的VDS相位寄存器，保持相移的FDS相位寄存器 FDS模式中的相位偏移量被设定为在VDS模式和FDS模式数据中的哪一个被采样的模式设定单元，根据模式设定单元的设定值，提供所选择的相移量作为采样位置，以及时钟相移单元，其根据移位量移位输入时钟信号的相位，并提供偏移输入时钟信号作为采样时钟。

8. 发明申请

US20050235313A1 Program information acquisition apparatus, program information acquisition method, and program information acquisition program 审中-公开
标题翻译：节目信息获取装置，节目信息获取方法和节目信息采集程序
公开(公告)号：US20050235313A1
公开(公告)日：2005-10-20
申请号：US11092990
申请日：2005-03-30
申请人： Akihito Yamada , Masayoshi Murayama , Hiroshi Kida , Nozomu Kikuchi , Hideyuki Uchiyama , Takanori Harada
发明人： Akihito Yamada , Masayoshi Murayama , Hiroshi Kida , Nozomu Kikuchi , Hideyuki Uchiyama , Takanori Harada
IPC分类号： H04N5/445 , H04N5/50 , H04N7/025 , H04N7/03 , H04N7/035
CPC分类号： H04N5/44543 , H04N7/16 , H04N21/4383 , H04N21/44222 , H04N21/4432 , H04N21/4532 , H04N21/4821 , H04N21/84
摘要： A program information acquisition apparatus includes a program information acquisition unit, a program information accumulation unit, and a program information acquisition determining unit. In this configuration, a start of an acquisition operation by the program information acquisition unit is determined based on an information accumulation status of the program information accumulation unit. Thus, program information distributed from a desired reception target can be accumulated as the latest information as much as possible. Since unneeded program information is not acquired, program information acquisition with high energy saving effects is made possible.
摘要翻译：节目信息获取装置包括节目信息获取单元，节目信息存储单元和节目信息获取确定单元。在该配置中，基于节目信息聚积单元的信息累积状态来确定节目信息获取单元的获取操作的开始。因此，可以尽可能多地累积从期望的接收目标分发的节目信息作为最新信息。由于不获取不需要的节目信息，所以能够节省高节能效果的节目信息获取成为可能。

9. 发明授权

US5032838A Variable length code parallel decoding apparatus and method 失效
标题翻译：可变长度码并行解码装置及方法
公开(公告)号：US5032838A
公开(公告)日：1991-07-16
申请号：US428287
申请日：1989-10-26
申请人： Masayoshi Murayama , Fumitaka Sato , Kensuke Adachi , Shigekazu Sumita
发明人： Masayoshi Murayama , Fumitaka Sato , Kensuke Adachi , Shigekazu Sumita
IPC分类号： H03M7/40 , H03M7/42
CPC分类号： H03M7/425
摘要： When a variable length code requires two cycles in decoding, portions of code bit strings serving as objects to be decoded in first and second cycles of the variable length code are caused to overlap each other. In the first cycle, a non-overlapping portion is determined as a decoded portion. A length of a code bit string actually decoded in the first cycle is determined as a length of the code bit string serving as the object to be decoded in the first cycle excluding the length of the overlapping portion so as to determine a start position of the code bit string serving as the object to be decoded in the second cycle.
摘要翻译：当可变长度代码在解码中需要两个周期时，引起用作可变长度码的第一和第二周期中要解码的对象的码位串的部分彼此重叠。在第一周期中，将非重叠部分确定为解码部分。在第一周期中实际解码的码位串的长度被确定为用作除了重叠部分的长度之外的第一周期中要解码的对象的码位串的长度，以便确定用作第二周期中要解码的对象的码位串。

10. 发明授权

US08214563B2 Host computer, computer terminal, and card access method 失效
标题翻译：主机，计算机终端和卡访问方式
公开(公告)号：US08214563B2
公开(公告)日：2012-07-03
申请号：US12823632
申请日：2010-06-25
申请人： Masayoshi Murayama
发明人： Masayoshi Murayama
IPC分类号： G06F3/00
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： According to one embodiment, the host controller includes a transmission circuit that encodes transmission data, according to a serial transfer format, a reception circuit that decodes received data, according to the serial transfer format, a variable frequency clock generator that generates a card clock and a transfer clock, a card clock output unit that outputs the card clock to the memory card, an interface unit includes a transmission interface that transfers the transmission data from the transmission circuit to the memory card in synchronization with the transfer clock, and a reception interface that transfers received data from the memory card to the reception circuit in synchronization with the transfer clock, and a setting register circuit that holds setting information concerning an input/output method of the memory card, and controls frequency of the transfer clock generated by the variable frequency clock generator, based on the setting information.
摘要翻译：根据一个实施例，主机控制器包括：传输电路，根据串行传输格式，根据串行传输格式对接收数据进行解码的接收电路，产生卡时钟的可变频率时钟发生器，以及传输时钟，将时钟输出到存储卡的卡时钟输出单元，接口单元包括传输接口，该传输接口与传输时钟同步地将传输数据从传输电路传送到存储卡;接收接口其将接收到的数据从存储卡传送到与传送时钟同步的接收电路，以及设置寄存器电路，其保存关于存储卡的输入/输出方法的设置信息，并且控制由变量产生的传送时钟的频率频率时钟发生器，基于设置信息。

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