专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5510639A Non-volatile semiconductor memory having a ring-shaped floating gate 失效
标题翻译：具有环形浮动栅极的非易失性半导体存储器
公开(公告)号：US5510639A
公开(公告)日：1996-04-23
申请号：US384791
申请日：1995-02-09
申请人： Yasushi Okuda , Yoshinori Odake , Ichiro Nakao , Youhei Ichikawa
发明人： Yasushi Okuda , Yoshinori Odake , Ichiro Nakao , Youhei Ichikawa
IPC分类号： H01L21/336 , H01L27/115 , H01L29/06 , H01L29/788 , H01L29/76
CPC分类号： H01L29/66825 , H01L27/115 , H01L29/0692 , H01L29/7885
摘要： A non-volatile semiconductor memory cell having a novel structure is provided. The memory cell has a ring-shaped channel region formed on a semiconductor substrate, a drain region formed in a zone surrounded by the channel region, and a source region formed outside the channel region. The cell further includes a first gate insulation layer formed on the substrate in such a manner as to cover the boundary between the channel region and the drain region, a ring-shaped floating gate electrode formed on the first gate insulation layer, a second gate insulation layer formed on the floating gate electrode; and a control gate electrode which is capacitive-coupled with the floating gate via the second gate insulation layer.
摘要翻译：提供具有新颖结构的非易失性半导体存储单元。存储单元具有形成在半导体衬底上的环形沟道区域，形成在由沟道区域包围的区域中的漏极区域和形成在沟道区域外部的源极区域。电池还包括以覆盖沟道区域和漏极区域之间的边界的方式形成在衬底上的第一栅极绝缘层，形成在第一栅极绝缘层上的环形浮栅电极，第二栅极绝缘层形成在浮栅电极上的层; 以及通过第二栅极绝缘层与浮动栅极电容耦合的控制栅电极。

2. 发明授权

US5715196A Method for driving a non-volatile semiconductor memory 失效
标题翻译：用于驱动非易失性半导体存储器的方法
公开(公告)号：US5715196A
公开(公告)日：1998-02-03
申请号：US684178
申请日：1996-07-19
申请人： Yoshinori Odake , Akira Asai , Yasushi Okuda , Toshiki Mori , Ichirou Nakao
发明人： Yoshinori Odake , Akira Asai , Yasushi Okuda , Toshiki Mori , Ichirou Nakao
IPC分类号： G11C16/04 , G11C16/26 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/26 , H01L27/115 , H01L29/66825 , H01L29/7883
摘要： An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.
摘要翻译：提供了排列成行和列的非易失性存储单元阵列。每个存储单元由由栅极，源极和漏极以及电容部分构成的晶体管构成。每个存储单元通过字线连接到行解码器，通过位线连接到列解码器，并通过源线连接到源解码器。在从位线延伸到源极线通过晶体管的路径中布置的是各向异性电阻部分，例如二极管，对于施加在其上的不同电压电平，具有不同的电压 - 电流特性。由于这样的布置，可以减少或可以消除在读取操作中对取消选择的存储单元发生的泄漏电流。可以避免由于泄漏电流而导致的读取错误，并且可以降低功耗。

3. 发明授权

US5627779A Non-volatile semiconductor memory having an array of non-volatile memory cells and method for driving the same 失效
标题翻译：具有非易失性存储单元阵列的非易失性半导体存储器及其驱动方法
公开(公告)号：US5627779A
公开(公告)日：1997-05-06
申请号：US505638
申请日：1995-07-21
申请人： Yoshinori Odake , Akira Asai , Yasushi Okuda , Toshiki Mori , Ichirou Nakao
发明人： Yoshinori Odake , Akira Asai , Yasushi Okuda , Toshiki Mori , Ichirou Nakao
IPC分类号： G11C16/04 , G11C16/26 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , G11C16/02
CPC分类号： H01L27/11521 , G11C16/0416 , G11C16/26 , H01L27/115 , H01L29/66825 , H01L29/7883
摘要： An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.
摘要翻译：提供了排列成行和列的非易失性存储单元阵列。每个存储单元由由栅极，源极和漏极以及电容部分构成的晶体管构成。每个存储单元通过字线连接到行解码器，通过位线连接到列解码器，并通过源线连接到源解码器。在从位线延伸到源极线通过晶体管的路径中布置的是各向异性电阻部分，例如二极管，对于施加在其上的不同电压电平，具有不同的电压 - 电流特性。由于这样的布置，可以减少或可以消除在读取操作中对取消选择的存储单元发生的泄漏电流。可以避免由于泄漏电流而导致的读取错误，并且可以降低功耗。

4. 发明授权

US5359554A Semiconductor memory device having an energy gap for high speed operation 失效
标题翻译：具有用于高速操作的能隙的半导体存储器件
公开(公告)号：US5359554A
公开(公告)日：1994-10-25
申请号：US906671
申请日：1992-06-30
申请人： Yoshinori Odake , Yasushi Okuda
发明人： Yoshinori Odake , Yasushi Okuda
IPC分类号： G11C17/00 , G11C16/02 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/861 , H01L27/10
CPC分类号： G11C16/0466 , G11C16/02 , H01L27/115 , H01L29/792 , H01L29/8616
摘要： A semiconductor device is provided comprising a nonvolatile memory cell through which an LSI and a higher operating speed are achieved. A drain region, an insulating layer partly overlaying the drain region, and a gate electrode formed on the insulating layer are formed on a semiconductor substrate thereby making up a memory cell without a source region. An energy gap between the conduction and valence bands of a semiconductor section including the drain region and the semiconductor substrate is preset to a value corresponding to a first set voltage difference between the drain and the gate. The energy gap between the valence bands (or the conduction bands) of the insulating layer and the semiconductor section at the interface between the semiconductor section and the insulating layer is preset to a value corresponding to a second set voltage difference between the drain and the substrate. Write operations are done by trapping in the insulating layer a charge which has jumped the valence band of the insulating layer at a voltage not less than the second set voltage difference. Read operations are done at a voltage not less than the first set voltage but not more than the second set voltage. Erase operations are done by releasing a charge trapped or by implanting a reverse charge.
摘要翻译：提供一种半导体器件，其包括非易失性存储单元，通过该非易失性存储单元实现LSI和更高的操作速度。漏极区域，部分覆盖漏极区域的绝缘层和形成在绝缘层上的栅电极形成在半导体衬底上，从而构成不具有源极区域的存储单元。包括漏极区域和半导体衬底的半导体区段的导通带和带隙之间的能隙被预设为对应于漏极和栅极之间的第一设定电压差的值。在半导体部分和绝缘层之间的界面处的绝缘层和半导体部分的价带（或导带）之间的能隙被预设为对应于漏极和衬底之间的第二设定电压差的值。写入操作是通过在绝缘层中俘获已经以不小于第二设定电压差的电压跳过绝缘层的价带的电荷来完成的。读操作以不低于第一设定电压但不大于第二设定电压的电压完成。擦除操作是通过释放被捕获的电荷或通过注入反向电荷来完成的。

5. 发明授权

US5640345A Semiconductor memory device and fabrication process 失效
标题翻译：半导体存储器件和制造工艺
公开(公告)号：US5640345A
公开(公告)日：1997-06-17
申请号：US679319
申请日：1996-07-12
申请人： Yasushi Okuda , Takashi Hori , Ichiro Nakao
发明人： Yasushi Okuda , Takashi Hori , Ichiro Nakao
IPC分类号： G11C11/56 , G11C16/04 , H01L27/108 , H01L27/115 , G11C11/40
CPC分类号： H01L27/11502 , G11C11/5657 , G11C11/5671 , G11C16/0416 , H01L27/108
摘要： Provided between a control gate electrode and a channel region of the EEPROM memory cell is a capacitor. Formed on the channel region are a first gate dielectric layer of silicon oxide, a first carrier capture layer of silicon nitride, a carrier migration layer of n.sup.31 polysilicon, a second carrier capture layer of silicon nitride, and a second gate dielectric layer of silicon oxide. The carrier capture state of the carrier capture layer is changed to generate a polarization state in the capacitor, and the generated polarization state is held as data. The gate dielectric layer is not destroyed since the movement of carriers is limited to within the capacitor, and by adjusting the carrier bound energy, low-voltage drive can be accomplished.
摘要翻译：在EEPROM存储单元的控制栅电极和沟道区之间设置有电容器。在沟道区上形成有第一栅极电介质层，氮化硅的第一载流子俘获层，n31多晶硅的载流子迁移层，氮化硅的第二载流子俘获层和氧化硅的第二栅极电介质层。载波俘获层的载波捕获状态被改变以在电容器中产生极化状态，并且所生成的极化状态被保持为数据。由于载流子的移动被限制在电容器内，并且通过调节载流子结合的能量，可以实现低压驱动，所以栅极介电层不被破坏。

6. 发明授权

US06472281B2 Method for fabricating semiconductor device using a CVD insulator film 有权
标题翻译：使用CVD绝缘膜制造半导体器件的方法
公开(公告)号：US06472281B2
公开(公告)日：2002-10-29
申请号：US09238584
申请日：1999-01-28
申请人： Hiroyuki Doi , Yasushi Okuda , Keita Takahashi , Nobuyuki Tamura
发明人： Hiroyuki Doi , Yasushi Okuda , Keita Takahashi , Nobuyuki Tamura
IPC分类号： H01L21336
CPC分类号： H01L29/66825 , H01L21/2652 , H01L21/28273 , H01L21/31612 , H01L29/6656 , H01L29/6659
摘要： A gate insulator film and a gate electrode are formed on an Si substrate, and a CVD insulator film is deposited thereon to cover the gate electrode. Then, arsenic ions are implanted into the Si substrate from above the CVD insulator film to form LDD layers. After sidewall spacers have been formed over the side faces of the gate electrode with the CVD insulator film interposed therebetween, source/drain layers are formed. Since the LDD layers are formed by implanting dopant ions through the CVD insulator film, the passage of arsenic ions through the ends of the gate electrode can be suppressed. As a result, a semiconductor device suitable for miniaturization can be formed, while suppressing deterioration in insulating properties of the gate oxide film due to the passage of dopant ions through the ends of the gate electrode.
摘要翻译：在Si衬底上形成栅极绝缘体膜和栅电极，并在其上沉积CVD绝缘膜以覆盖栅电极。然后，从CVD绝缘膜上方将砷离子注入Si衬底中以形成LDD层。在栅电极的侧面上形成有侧壁间隔物之后，CVD绝缘体膜之间形成有源极/漏极层。由于通过CVD绝缘膜注入掺杂剂离子形成LDD层，因此能够抑制砷离子通过栅电极的端部。结果，可以形成适合于小型化的半导体器件，同时抑制由于掺杂剂离子通过栅电极的端部而导致的栅极氧化膜的绝缘性能的劣化。

7. 发明授权

US06753222B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06753222B2
公开(公告)日：2004-06-22
申请号：US10271879
申请日：2002-10-15
申请人： Ken Mimuro , Hiroyuki Doi , Yasushi Okuda
发明人： Ken Mimuro , Hiroyuki Doi , Yasushi Okuda
IPC分类号： H01L21336
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11534
摘要： A method for forming a semiconductor device is provided that allows a desirable semiconductor device to be obtained by preventing a gate electrode of a non-volatile semiconductor memory from having an abnormal shape and the surfaces of high concentration source and drain regions of the non-volatile semiconductor memory from being worn away. The method includes a first step of forming a non-volatile semiconductor memory in a first region of a substrate of the semiconductor device and a second step of forming a semiconductor device in a second region on the substrate. The non-volatile semiconductor memory includes a first gate including a tunnel insulating film, a floating gate electrode, a capacitor insulating film, and a control gate electrode, and the semiconductor device includes a second gate including a gate insulating film and a gate electrode. In this method, during patterning of the second gate, a surface of the first gate is covered with a protective film that hardly can be etched by an etchant used for the patterning of the second gate.
摘要翻译：提供一种用于形成半导体器件的方法，其通过防止非易失性半导体存储器的栅电极具有异常形状并且使非挥发性的高浓度源极和漏极区域的表面能够获得期望的半导体器件半导体存储器被磨损掉。该方法包括在半导体器件的衬底的第一区域中形成非易失性半导体存储器的第一步骤和在衬底上的第二区域中形成半导体器件的第二步骤。非易失性半导体存储器包括：第一栅极，其包括隧道绝缘膜，浮栅电极，电容绝缘膜和控制栅电极，并且所述半导体器件包括包括栅极绝缘膜和栅电极的第二栅极。在该方法中，在图案化第二栅极期间，第一栅极的表面被几乎不能被用于第二栅极图案化的蚀刻剂所蚀刻的保护膜覆盖。

8. 发明授权

US4657591A Ink composition 失效
标题翻译：墨水组成
公开(公告)号：US4657591A
公开(公告)日：1987-04-14
申请号：US590913
申请日：1984-03-15
申请人： Keiko Shioi , Yasushi Okuda
发明人： Keiko Shioi , Yasushi Okuda
IPC分类号： C09D11/00 , B65H54/02 , B65H54/70 , B65H67/056 , C09D11/10 , C09D11/16
CPC分类号： C09D11/17
摘要： An ink composition for writing on an absorbent or pervious writing surface to form thereon a writing or marking composed of an inner portion of a metallic color with outer contour portions therearound of a dyestuff-based color, which composition comprises:a nonleafing metal powder pigment as a first pigment,an inorganic or organic pigment as a second pigment,a dyestuff, anda solvent,the nonleafing metal powder pigment being dispersed in the solvent and having a particle size sufficiently large so as to substantially not permeate or be absorbed into the writing surface, andthe second pigment being dispersed in the solvent and either having a particle size sufficiently large so as to substantially not permeate or be absorbed into the writing surface, or having a particle size sufficiently large so as to substantially be adsorbed on the nonleafing metal powder pigment,the dyestuff being dissolved in the solvent, being capable of substantially permeating or being absorbed into the writing surface and diffusing into the area on the writing surface proximate to the writing,whereby the nonleafing metal powder pigment forms in conjunction with the second pigment the inner portion of the metallic color, and the dyestuff forms the outer contour portions of the dyestuff-based color around the inner portion.
摘要翻译：一种用于在吸收性或可渗透的书写表面上书写的油墨组合物，以在其上形成由金属颜色的内部部分组成的书写或标记，其中包含基于染料的颜色的外部轮廓部分，该组合物包括：非底漆金属粉末颜料第一颜料，作为第二颜料的无机或有机颜料，染料和溶剂，非漂洗性金属粉末颜料分散在溶剂中并且具有足够大的粒径，以便基本上不渗透或被吸收到书写中表面，并且第二颜料分散在溶剂中，并且具有足够大的粒度，以便基本上不渗透或被吸收到书写表面，或者具有足够大的粒度以便基本上被吸附在非擦洗金属上粉末颜料，染料溶于溶剂中，能够基本渗透或吸收到w中在书写表面附近扩散到书写表面上的区域，由此非擦洗金属粉末颜料与第二颜料一起形成金属颜色的内部，染料形成基于染料的外部轮廓部分颜色围绕内部。

9. 发明授权

US06657893B2 Nonvolatile semiconductor memory device and method for driving the same 有权
公开(公告)号：US06657893B2
公开(公告)日：2003-12-02
申请号：US10050965
申请日：2002-01-22
申请人： Keita Takahashi , Masafumi Doi , Hiroyuki Doi , Nobuyuki Tamura , Yasushi Okuda
发明人： Keita Takahashi , Masafumi Doi , Hiroyuki Doi , Nobuyuki Tamura , Yasushi Okuda
IPC分类号： G11C1604
CPC分类号： G11C16/0416 , G11C16/0433 , H01L27/115
摘要： A memory transistor and a select transistor are disposed side by side on a semiconductor substrate between source/drain diffusion layers thereof, with an intermediate diffusion layer interposed therebetween. The memory transistor includes: a gate insulating film having such a thickness as to allow tunneling current to pass therethrough; a floating gate electrode; an interelectrode insulating film; and a control gate electrode. The select transistor includes a gate insulating film and a select gate electrode. Tunneling current, allowing electrons to pass through the gate insulating film under the floating gate electrode, is utilized during the removal and injection of electrons from/into the floating gate electrode. As a result, higher reliability can be attained and rewriting can be performed at a lower voltage. Also, since the select transistor is provided, reading can also be performed at a lower voltage. Improvement of reliability and rewrite and read operations at respective lower voltages are realized for a nonvolatile semiconductor memory device, in which a memory cell includes a floating gate electrode and a control gate electrode.

10. 发明授权

US6005401A Semiconductor wafer package, method and apparatus for connecting testing IC terminals of semiconductor wafer and probe terminals, testing method of a semiconductor integrated circuit, probe card and its manufacturing method 失效
标题翻译：用于连接半导体晶片和探针端子的IC端子的半导体晶片封装，方法和装置，半导体集成电路的测试方法，探针卡及其制造方法
公开(公告)号：US6005401A
公开(公告)日：1999-12-21
申请号：US837954
申请日：1997-04-14
申请人： Yoshirou Nakata , Toshio Yamada , Atsushi Fujiwara , Isao Miyanaga , Shin Hashimoto , Yukiharu Uraoka , Yasushi Okuda , Kenzou Hatada
发明人： Yoshirou Nakata , Toshio Yamada , Atsushi Fujiwara , Isao Miyanaga , Shin Hashimoto , Yukiharu Uraoka , Yasushi Okuda , Kenzou Hatada
IPC分类号： G01R1/04 , G01R1/073 , G01R31/28 , H01L21/66
CPC分类号： G01R31/2886 , G01R1/0491 , G01R31/2867 , G01R31/2831
摘要： A retainer board, holding a semiconductor wafer having a plurality of integrated circuit terminals for testing a semiconductor chip, is provided in confronting relation to a probe sheet having a plurality of probe terminals electrically connected to their corresponding integrated circuit terminals. An insulating substrate, having wiring electrically connected to the plural probe terminals, is provided on the probe sheet in opposed relation to the retainer board. An elastic member is interposed between the probe sheet and the insulating substrate. The retainer board and the probe sheet are brought into so closer relationship that each integrated circuit terminal of the semiconductor wafer held by the retainer board is electrically connected to its corresponding probe terminal of the probe sheet.
摘要翻译：提供了一种保持板，其具有多个用于测试半导体芯片的集成电路端子的半导体晶片，与具有电连接到其相应的集成电路端子的多个探针端子的探针片相对。具有与多个探针端子电连接的布线的绝缘基板设置在与保持板相对的探针片上。在探针片和绝缘基片之间插入弹性部件。保持板和探针片的关系使得由保持板保持的半导体晶片的每个集成电路端子电连接到其对应的探针片的探针端子。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式