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1. 发明申请

US20100161881A1 MEMORY SYSTEM 审中-公开
标题翻译：记忆系统
公开(公告)号：US20100161881A1
公开(公告)日：2010-06-24
申请号：US12529473
申请日：2009-03-03
申请人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
发明人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
IPC分类号： G06F12/02
CPC分类号： G06F11/1016 , G06F12/0246 , G06F2212/7203 , G06F2212/7209 , G11C16/102
摘要： A memory system (10) is disclosed, which comprises a flash-EEPROM nonvolatile memory (11) having a plurality of memory cells that have floating gates and in which data items are electrically erasable and writable, a cache memory (13) that temporarily stores data of the flash-EEPROM nonvolatile memory (11), a control circuit (12, 14) that controls the flash-EEPROM nonvolatile memory (11) and the cache memory (13), and an interface circuit (16) that communicates with a host, in which the control circuit functions to read data from a desired target area to-be-determined of the flash-EEPROM nonvolatile memory and detect an erased area to determine a written area/unwritten area by using as a determination condition whether or not a count number of data “0” of the read data has reached a preset criterion count number.
摘要翻译：一种存储系统（10），其包括具有多个存储单元的闪存EEPROM非易失性存储器（11），所述多个存储器单元具有浮动栅极，并且其中数据项是电可擦除和可写的;高速缓冲存储器（13），其临时存储闪存EEPROM非易失性存储器（11）的数据，控制闪存EEPROM非易失性存储器（11）和高速缓存存储器（13）的控制电路（12,14）以及与主机，其中控制电路用于从要被确定的闪存EEPROM非易失性存储器的期望目标区域读取数据，并且通过使用作为确定条件来检测擦除区域以确定写入区域/未写入区域读取数据的数据“0”的计数数已经达到预设的标准计数。

2. 发明申请

US20100107021A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20100107021A1
公开(公告)日：2010-04-29
申请号：US12523607
申请日：2008-09-30
申请人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
发明人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
IPC分类号： G11C29/52 , G06F11/10
CPC分类号： G11C16/349 , G06F11/1068 , G11C11/005 , G11C16/3431
摘要： This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.
摘要翻译：本公开涉及存储器，包括：包括存储器组的第一存储器区域，包括多个存储器单元，分别分配给存储器组的地址，存储器组分别是数据擦除操作的单位; 第二存储器区域暂时存储从第一存储器区域读取的数据或者暂时存储要写入到第一存储器区域的数据; 读取计数器，存储每个存储器组的数据读取计数; 错误校正电路，计算读取数据的错误位数; 以及执行刷新操作的控制器，其中存储在一个存储器组中的读取数据被临时存储在第二存储器区域中，并且当读取数据写入同一存储器组时，当错误位计数超过第一阈值时或者当数据读取计数超过第二阈值时。

3. 发明授权

US08255762B2 Semiconductor memory device with error correction 有权
标题翻译：具有误差校正的半导体存储器件
公开(公告)号：US08255762B2
公开(公告)日：2012-08-28
申请号：US13297327
申请日：2011-11-16
申请人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
发明人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
IPC分类号： H03M13/00
CPC分类号： G11C16/349 , G06F11/1068 , G11C11/005 , G11C16/3431
摘要： This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.
摘要翻译：本公开涉及存储器，包括：包括存储器组的第一存储器区域，包括多个存储器单元，分别分配给存储器组的地址，存储器组分别是数据擦除操作的单位; 第二存储器区域暂时存储从第一存储器区域读取的数据或者暂时存储要写入到第一存储器区域的数据; 读取计数器，存储每个存储器组的数据读取计数; 错误校正电路，计算读取数据的错误位数; 以及执行刷新操作的控制器，其中存储在一个存储器组中的读取数据被临时存储在第二存储器区域中，并且当读取的数据被写回同一个存储器组时，当错误位计数超过第一阈值时或者当数据读取计数超过第二阈值时。

4. 发明授权

US08156393B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US08156393B2
公开(公告)日：2012-04-10
申请号：US12513860
申请日：2007-11-28
申请人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda , Shinichi Kanno
发明人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda , Shinichi Kanno
IPC分类号： G11C29/00
CPC分类号： G11C16/349 , G06F11/008 , G06F11/1068
摘要： To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.
摘要翻译：提供一种确定诸如耗尽水平的存储器状态并且允许有效地使用存储器的存储器系统。存储器系统包括NAND型闪速存储器1，数据可以被电写入/擦除;非易失性存储器2，对NAND型闪速存储器1的擦除操作次数进行计数，并保持擦除次数和最大数量擦除操作，以及控制器3，其具有从计算机4被给予自诊断命令的连接接口31，并且基于自身检测从非易失性存储器2检索擦除操作的次数和擦除操作的最大次数，诊断命令，并通过连接接口31输出擦除操作次数和最大擦除次数。

5. 发明授权

US08078923B2 Semiconductor memory device with error correction 有权
标题翻译：具有误差校正的半导体存储器件
公开(公告)号：US08078923B2
公开(公告)日：2011-12-13
申请号：US12523607
申请日：2008-09-30
申请人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
发明人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
IPC分类号： G06F11/00
CPC分类号： G11C16/349 , G06F11/1068 , G11C11/005 , G11C16/3431
摘要： This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.
摘要翻译：本公开涉及存储器，包括：包括存储器组的第一存储器区域，包括多个存储器单元，分别分配给存储器组的地址，存储器组分别是数据擦除操作的单位; 第二存储器区域暂时存储从第一存储器区域读取的数据或者暂时存储要写入到第一存储器区域的数据; 读取计数器，存储每个存储器组的数据读取计数; 错误校正电路，计算读取数据的错误位数; 以及执行刷新操作的控制器，其中存储在一个存储器组中的读取数据被临时存储在第二存储器区域中，并且当读取数据写入同一存储器组时，当错误位计数超过第一阈值时或者当数据读取计数超过第二阈值时。

6. 发明申请

US20100011260A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20100011260A1
公开(公告)日：2010-01-14
申请号：US12513860
申请日：2007-11-28
申请人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda , Shinichi Kanno
发明人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda , Shinichi Kanno
IPC分类号： G11C29/04 , G06F11/22 , G06F11/00
CPC分类号： G11C16/349 , G06F11/008 , G06F11/1068
摘要： To provide a memory system which determines a memory state such as an exhaustion level and allows a memory to be efficiently used.The memory system includes a NAND type flash memory 1 in which data can be electrically written/erased, a nonvolatile memory 2 which counts the number of erase operations of the NAND type flash memory 1 and retains the number of erase operations and a maximum number of erase operations, and a controller 3 which has a connection interface 31 to be given a self-diagnosis command from a computer 4, and retrieves the number of erase operations and the maximum number of erase operations from the nonvolatile memory 2 based on the self-diagnosis command and outputs the number of erase operations and the maximum number of erase operations to the computer 4 through the connection interface 31.
摘要翻译：提供一种确定诸如耗尽水平的存储器状态并且允许有效地使用存储器的存储器系统。存储器系统包括NAND型闪速存储器1，数据可以被电写入/擦除;非易失性存储器2，对NAND型闪速存储器1的擦除操作次数进行计数，并保持擦除次数和最大数量擦除操作，以及控制器3，其具有从计算机4被给予自诊断命令的连接接口31，并且基于自身检测从非易失性存储器2检索擦除操作的次数和擦除操作的最大次数，诊断命令，并通过连接接口31输出擦除操作次数和最大擦除次数。

7. 发明申请

US20120060066A1 SEMICONDUCTOR MEMORY DEVICE WITH ERROR CORRECTION 有权
标题翻译：具有错误校正的半导体存储器件
公开(公告)号：US20120060066A1
公开(公告)日：2012-03-08
申请号：US13297327
申请日：2011-11-16
申请人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
发明人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
IPC分类号： G06F11/16
CPC分类号： G11C16/349 , G06F11/1068 , G11C11/005 , G11C16/3431
摘要： This disclosure concerns a memory including: a first memory region including memory groups including a plurality of memory cells, addresses being respectively allocated for the memory groups, the memory groups respectively being units of data erase operations; a second memory region temporarily storing therein data read from the first memory region or temporarily storing therein data to be written to the first memory region; a read counter storing therein a data read count for each memory group; an error-correcting circuit calculating an error bit count of the read data; and a controller performing a refresh operation, in which the read data stored in one of the memory groups is temporarily stored in the second memory region and is written back the read data to the same memory group, when the error bit count exceeds a first threshold or when the data read count exceeds a second threshold.
摘要翻译：本公开涉及存储器，包括：包括存储器组的第一存储器区域，包括多个存储器单元，分别分配给存储器组的地址，存储器组分别是数据擦除操作的单位; 第二存储器区域暂时存储从第一存储器区域读取的数据或者暂时存储要写入到第一存储器区域的数据; 读取计数器，存储每个存储器组的数据读取计数; 错误校正电路，计算读取数据的错误位数; 以及执行刷新操作的控制器，其中存储在一个存储器组中的读取数据被临时存储在第二存储器区域中，并且当读取的数据被写回同一个存储器组时，当错误位计数超过第一阈值时或者当数据读取计数超过第二阈值时。

8. 发明授权

US08484432B2 Memory system 有权
标题翻译：内存系统
公开(公告)号：US08484432B2
公开(公告)日：2013-07-09
申请号：US12401130
申请日：2009-03-10
申请人： Kosuke Hatsuda , Daisaburo Takashima , Yasushi Nagadomi
发明人： Kosuke Hatsuda , Daisaburo Takashima , Yasushi Nagadomi
IPC分类号： G06F12/00
CPC分类号： G06F12/0866 , G06F2212/2022
摘要： A memory system includes a non-volatile memory constituted by blocks each of which is an erase unit constituted by pages each of which is a write/read unit constituted by memory cells; a random access memory temporarily storing data which is written in or read from the non-volatile memory; and a controller controlling the non-volatile memory and the random access memory, wherein the non-volatile memory includes a main memory area in which the block is divided into first management units respectively specified by logical addresses and a cache area in which the block is divided into second management units respectively specified by logical addresses, a data capacity of one of the second management units is smaller than that of one of the first management units, and the controller changes number of the blocks in the main memory area and number of the blocks in the cache area in the non-volatile memory.
摘要翻译：存储器系统包括由块构成的非易失性存储器，每个存储器是由存储单元构成的写入/读取单元的页面构成的擦除单元; 临时存储写入或从非易失性存储器读取的数据的随机存取存储器; 以及控制非易失性存储器和随机存取存储器的控制器，其中所述非易失性存储器包括主存储区域，其中所述块被划分为分别由逻辑地址指定的第一管理单元和所述块为分为由逻辑地址分别指定的第二管理单元，其中一个第二管理单元的数据容量小于第一管理单元之一的数据容量，并且控制器改变主存储器区域中的块数量和在非易失性存储器中的缓存区域中的块。

9. 发明授权

US07778078B2 Memory system and control method thereof 有权
标题翻译：存储系统及其控制方法
公开(公告)号：US07778078B2
公开(公告)日：2010-08-17
申请号：US12019227
申请日：2008-01-24
申请人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
发明人： Yasushi Nagadomi , Daisaburo Takashima , Kosuke Hatsuda
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/005 , G11C16/3431 , G11C16/3436
摘要： A memory system includes: a flash memory that stores data; a memory that stores a read count table that indicates the number of times of data read from the flash memory; and a controller that performs: reading out the data from the flash memory; updating the read count table when the controller performs reading out the data from the flash memory; and refreshing the flash memory based on the read count table.
摘要翻译：存储器系统包括：存储数据的闪速存储器; 存储器，其存储指示从闪存读取的数据的次数的读取计数表; 以及控制器，执行：从所述闪存读出数据; 当控制器执行从闪速存储器读出数据时更新读取计数表; 并根据读取计数表刷新闪存。

10. 发明申请

US20090235015A1 MEMORY SYSTEM 有权
标题翻译：记忆系统
公开(公告)号：US20090235015A1
公开(公告)日：2009-09-17
申请号：US12401130
申请日：2009-03-10
申请人： Kosuke Hatsuda , Daisaburo Takashima , Yasushi Nagadomi
发明人： Kosuke Hatsuda , Daisaburo Takashima , Yasushi Nagadomi
IPC分类号： G06F12/00 , G06F12/02 , G06F12/08
CPC分类号： G06F12/0866 , G06F2212/2022
摘要： A memory system includes a non-volatile memory constituted by blocks each of which is an erase unit constituted by pages each of which is a write/read unit constituted by memory cells; a random access memory temporarily storing data which is written in or read from the non-volatile memory; and a controller controlling the non-volatile memory and the random access memory, wherein the non-volatile memory includes a main memory area in which the block is divided into first management units respectively specified by logical addresses and a cache area in which the block is divided into second management units respectively specified by logical addresses, a data capacity of one of the second management units is smaller than that of one of the first management units, and the controller changes number of the blocks in the main memory area and number of the blocks in the cache area in the non-volatile memory.
摘要翻译：存储器系统包括由块构成的非易失性存储器，每个存储器是由存储单元构成的写入/读取单元的页面构成的擦除单元; 临时存储写入或从非易失性存储器读取的数据的随机存取存储器; 以及控制非易失性存储器和随机存取存储器的控制器，其中所述非易失性存储器包括主存储区域，其中所述块被划分为分别由逻辑地址指定的第一管理单元和所述块为分为由逻辑地址分别指定的第二管理单元，其中一个第二管理单元的数据容量小于第一管理单元之一的数据容量，并且控制器改变主存储器区域中的块数量和在非易失性存储器中的缓存区域中的块。

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