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1. 发明授权

US08148778B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08148778B2
公开(公告)日：2012-04-03
申请号：US13050496
申请日：2011-03-17
申请人： Yasushi Kobayashi , Manabu Imahashi
发明人： Yasushi Kobayashi , Manabu Imahashi
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/0878 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.
摘要翻译：半导体器件包括：n型第一阱扩散层; n型第二阱扩散层; p型源极扩散层; p型第三阱扩散层; p型漏极扩散层; 栅极绝缘膜; 栅电极; 器件隔离绝缘膜; 和缓冲层。缓冲层形成在第一阱扩散层和第三阱扩散层之间，以与第三阱扩散层的与源极扩散层相对的端部接触，并且从栅绝缘膜的正下方延伸到比第第三阱扩散层的杂质浓度分布的曲率峰值。缓冲层的杂质浓度低于第三阱扩散层中的杂质浓度。

2. 发明授权

US07932558B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07932558B2
公开(公告)日：2011-04-26
申请号：US12424119
申请日：2009-04-15
申请人： Yasushi Kobayashi , Manabu Imahashi
发明人： Yasushi Kobayashi , Manabu Imahashi
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L29/0878 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.
摘要翻译：半导体器件包括：n型第一阱扩散层; n型第二阱扩散层; p型源极扩散层; p型第三阱扩散层; p型漏极扩散层; 栅极绝缘膜; 栅电极; 器件隔离绝缘膜; 和缓冲层。缓冲层形成在第一阱扩散层和第三阱扩散层之间，以与第三阱扩散层的与源极扩散层相对的端部接触，并且从栅绝缘膜的正下方延伸到比第第三阱扩散层的杂质浓度分布的曲率峰值。缓冲层的杂质浓度低于第三阱扩散层中的杂质浓度。

3. 发明申请

US20110163377A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110163377A1
公开(公告)日：2011-07-07
申请号：US13050496
申请日：2011-03-17
申请人： Yasushi KOBAYASHI , Manabu Imahashi
发明人： Yasushi KOBAYASHI , Manabu Imahashi
IPC分类号： H01L29/78
CPC分类号： H01L29/0878 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.
摘要翻译：半导体器件包括：n型第一阱扩散层; n型第二阱扩散层; p型源极扩散层; p型第三阱扩散层; p型漏极扩散层; 栅极绝缘膜; 栅电极; 器件隔离绝缘膜; 和缓冲层。缓冲层形成在第一阱扩散层和第三阱扩散层之间，以与第三阱扩散层的与源极扩散层相对的端部接触，并且从栅绝缘膜的正下方延伸到比第第三阱扩散层的杂质浓度分布的曲率峰值。缓冲层的杂质浓度低于第三阱扩散层中的杂质浓度。

4. 发明申请

US20090267144A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090267144A1
公开(公告)日：2009-10-29
申请号：US12424119
申请日：2009-04-15
申请人： Yasushi KOBAYASHI , Manabu Imahashi
发明人： Yasushi KOBAYASHI , Manabu Imahashi
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/0878 , H01L29/0847 , H01L29/1045 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7835
摘要： A semiconductor device includes: an n-type first well diffusion layer; an n-type second well diffusion layer; a p-type source diffusion layer; a p-type third well diffusion layer; a p-type drain diffusion layer; a gate insulating film; a gate electrode; a device isolation insulating film; and a buffer layer. The buffer layer is formed between the first well diffusion layer and the third well diffusion layer to be in contact with an end of the third well diffusion layer opposing the source diffusion layer, and extends from immediately below the gate insulating film to a position deeper than a peak of curvature of impurity concentration distribution of the third well diffusion layer. The buffer layer has an impurity concentration lower than an impurity concentration in the third well diffusion layer.
摘要翻译：半导体器件包括：n型第一阱扩散层; n型第二阱扩散层; p型源极扩散层; p型第三阱扩散层; p型漏极扩散层; 栅极绝缘膜; 栅电极; 器件隔离绝缘膜; 和缓冲层。缓冲层形成在第一阱扩散层和第三阱扩散层之间，以与第三阱扩散层的与源极扩散层相对的端部接触，并且从栅绝缘膜的正下方延伸到比第第三阱扩散层的杂质浓度分布的曲率峰值。缓冲层的杂质浓度低于第三阱扩散层中的杂质浓度。

5. 发明申请

US20070210419A1 Electrostatic discharge protection device in integrated circuit 审中-公开
标题翻译：集成电路中的静电放电保护装置
公开(公告)号：US20070210419A1
公开(公告)日：2007-09-13
申请号：US11715406
申请日：2007-03-08
申请人： Masakatsu Nawate , Manabu Imahashi
发明人： Masakatsu Nawate , Manabu Imahashi
IPC分类号： H01L27/082 , H01L27/102
CPC分类号： H01L27/0259 , H01L29/735
摘要： An electrostatic discharge protection device of a semiconductor integrated circuit, comprising a first diffusion layer that is a diffusion layer of a second conductivity type provided on a semiconductor substrate of a first conductivity type and serves as a collector, a second diffusion layer that is a diffusion layer of the first conductivity type provided in the first diffusion layer and serves as a base, a third diffusion layer that is a diffusion layer of the second conductivity type provided in the second diffusion layer and serves as an emitter, a collector contact region provided in the first diffusion layer, a fourth diffusion layer that is a diffusion layer of the second conductivity type provided in the first diffusion layer in a downward region of the collector contact region in a substrate-thickness direction, wherein the fourth diffusion layer is formed shallower in a depth than that of the first diffusion layer in the substrate-thickness direction, deeper in a depth than that of the second diffusion layer in the substrate-thickness direction and with a high density than that of the first diffusion layer, and an insulation film formed on a surface of the first diffusion layer between the second diffusion layer and the collector contact region and serving as a field, wherein the fourth diffusion layer is extended up until a region below the insulation film.
摘要翻译：一种半导体集成电路的静电放电保护装置，包括：第一导电类型的扩散层的第一扩散层，设置在第一导电类型的半导体基板上并用作集电极;第二扩散层，其为扩散第一导电类型的层，设置在第一扩散层中并用作基底;第三扩散层，其是设置在第二扩散层中并用作发射极的第二导电类型的扩散层，设置在第二扩散层中的集电极接触区域第一扩散层，第四扩散层，其是在基板厚度方向上在集电极接触区域的向下区域中设置在第一扩散层中的第二导电类型的扩散层，其中第四扩散层形成为较浅比衬底厚度方向上的第一扩散层的深度更深，深度大于第二扩散层在基板厚度方向上的密度高于第一扩散层的第二扩散层，以及形成在第二扩散层和集电极接触区域之间的第一扩散层的表面上的绝缘膜，作为场，其中第四扩散层延伸直到绝缘膜下方的区域。

6. 发明授权

US07202531B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07202531B2
公开(公告)日：2007-04-10
申请号：US11085208
申请日：2005-03-22
申请人： Manabu Imahashi , Hiroyoshi Ogura , Masakatsu Nawate
发明人： Manabu Imahashi , Hiroyoshi Ogura , Masakatsu Nawate
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an output pad and a surge absorption unit formed above a semiconductor region of a first conductivity type. The surge absorption unit includes: a semiconductor island region of a second conductivity type; a buried layer of the second conductivity type formed between a bottom of the semiconductor island region of the second conductivity type and the semiconductor region of the first conductivity type; a dopant layer of the first conductivity type formed in an upper portion of the semiconductor island region of the second conductivity type and connected to have the same potential as the semiconductor region of the first conductivity type; a dopant layer of the second conductivity type formed in an upper portion of the dopant layer of the first conductivity type and electrically connected to the output pad; and a ring layer of the second conductivity type surrounding the dopant layer of the first conductivity type and reaching the buried layer of the second conductivity type. In this device, the ring layer of the second conductivity type is electrically connected to a terminal with a fixed potential and contains a dopant of the second conductivity type having a higher concentration than the semiconductor island region of the second conductivity type.
摘要翻译：半导体器件包括形成在第一导电类型的半导体区域上方的输出焊盘和浪涌吸收单元。浪涌吸收单元包括：第二导电类型的半导体岛区; 形成在第二导电类型的半导体岛区域的底部和第一导电类型的半导体区域之间的第二导电类型的掩埋层; 第一导电类型的掺杂剂层形成在第二导电类型的半导体岛区的上部并且具有与第一导电类型的半导体区相同的电位; 第二导电类型的掺杂剂层形成在第一导电类型的掺杂剂层的上部并电连接到输出焊盘; 以及围绕第一导电类型的掺杂剂层并到达第二导电类型的掩埋层的第二导电类型的环层。在该装置中，第二导电类型的环层与具有固定电位的端子电连接，并且包含具有比第二导电类型的半导体岛区域更高的浓度的第二导电类型的掺杂剂。

7. 发明授权

US07821029B2 Electrostatic protection element 有权
标题翻译：静电保护元件
公开(公告)号：US07821029B2
公开(公告)日：2010-10-26
申请号：US12542998
申请日：2009-08-18
申请人： Manabu Imahashi
发明人： Manabu Imahashi
IPC分类号： H01L29/74
CPC分类号： H01L29/7322 , H01L27/0262 , H01L29/7436
摘要： An electrostatic protection element relating to the present invention comprises a P-type semiconductor and an N-type first impurity layer provided in the semiconductor substrate. The first impurity layer comprises a P-type second impurity layer functioning as a gate. The second impurity layer comprises an N-type third impurity layer functioning as a cathode. Further, the first impurity layer comprises an N-type fourth impurity layer spaced apart from the second impurity layer at a distance. The fourth impurity layer comprises a P-type fifth impurity layer functioning as an anode and an N-type sixth impurity layer. Then, in the electrostatic protection element, an impurity concentration of the fourth impurity layer is higher than that of the first impurity layer, and a bottom of the fourth impurity layer is deeper than that of the second impurity layer.
摘要翻译：涉及本发明的静电保护元件包括设置在半导体衬底中的P型半导体和N型第一杂质层。第一杂质层包括用作栅极的P型第二杂质层。第二杂质层包括用作阴极的N型第三杂质层。此外，第一杂质层包括与第二杂质层间隔一定距离的N型第四杂质层。第四杂质层包括用作阳极的P型第五杂质层和N型第六杂质层。然后，在静电保护元件中，第四杂质层的杂质浓度高于第一杂质层的杂质浓度，第四杂质层的底部比第二杂质层的深。

8. 发明申请

US20050230761A1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US20050230761A1
公开(公告)日：2005-10-20
申请号：US11085208
申请日：2005-03-22
申请人： Manabu Imahashi , Hiroyoshi Ogura , Masakatsu Nawate
发明人： Manabu Imahashi , Hiroyoshi Ogura , Masakatsu Nawate
IPC分类号： H01L23/60 , H01L23/62 , H01L27/02 , H01L27/04 , H01L29/76
CPC分类号： H01L27/0262 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an output pad and a surge absorption unit formed above a semiconductor region of a first conductivity type. The surge absorption unit includes: a semiconductor island region of a second conductivity type; a buried layer of the second conductivity type formed between a bottom of the semiconductor island region of the second conductivity type and the semiconductor region of the first conductivity type; a dopant layer of the first conductivity type formed in an upper portion of the semiconductor island region of the second conductivity type and connected to have the same potential as the semiconductor region of the first conductivity type; a dopant layer of the second conductivity type formed in an upper portion of the dopant layer of the first conductivity type and electrically connected to the output pad; and a ring layer of the second conductivity type surrounding the dopant layer of the first conductivity type and reaching the buried layer of the second conductivity type. In this device, the ring layer of the second conductivity type is electrically connected to a terminal with a fixed potential and contains a dopant of the second conductivity type having a higher concentration than the semiconductor island region of the second conductivity type.
摘要翻译：半导体器件包括形成在第一导电类型的半导体区域上方的输出焊盘和浪涌吸收单元。浪涌吸收单元包括：第二导电类型的半导体岛区; 形成在第二导电类型的半导体岛区域的底部和第一导电类型的半导体区域之间的第二导电类型的掩埋层; 第一导电类型的掺杂剂层形成在第二导电类型的半导体岛区的上部并且具有与第一导电类型的半导体区相同的电位; 第二导电类型的掺杂剂层形成在第一导电类型的掺杂剂层的上部并电连接到输出焊盘; 以及围绕第一导电类型的掺杂剂层并到达第二导电类型的掩埋层的第二导电类型的环层。在该装置中，第二导电类型的环层与具有固定电位的端子电连接，并且包含具有比第二导电类型的半导体岛区域更高的浓度的第二导电类型的掺杂剂。

9. 发明授权

US08188568B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08188568B2
公开(公告)日：2012-05-29
申请号：US13022035
申请日：2011-02-07
申请人： Manabu Imahashi
发明人： Manabu Imahashi
IPC分类号： H01L21/70
CPC分类号： H01L29/732 , H01L27/0259 , H01L29/0821
摘要： A semiconductor circuit includes: a first diffusion layer formed on a substrate; a second diffusion layer formed in an upper part of the first diffusion layer; a third diffusion layer formed in an upper part of the second diffusion layer; a fourth diffusion layer formed in the upper part of the first diffusion layer; and a fifth diffusion formed below the third diffusion layer. A sum of a shortest distance from the third diffusion layer to the fifth diffusion layer and a shortest distance from the fifth diffusion layer or the lower end of the first diffusion layer to the fourth diffusion layer is smaller than a shortest distance from the third diffusion layer to the fourth diffusion layer. The substrate, the second and the fifth diffusion layer are a first conductivity type and the others are a second conductivity type.
摘要翻译：半导体电路包括：形成在基板上的第一扩散层; 形成在所述第一扩散层的上部的第二扩散层; 形成在第二扩散层的上部的第三扩散层; 形成在第一扩散层的上部的第四扩散层; 以及形成在第三扩散层下面的第五扩散层。从第三扩散层到第五扩散层的最短距离和从第一扩散层的第五扩散层或下端到第四扩散层的最短距离的距离小于距离第三扩散层的最短距离到第四扩散层。基板，第二和第五扩散层是第一导电类型，其它是第二导电类型。

10. 发明授权

US5142348A Lateral thyristor 失效
标题翻译：横向晶闸管
公开(公告)号：US5142348A
公开(公告)日：1992-08-25
申请号：US566520
申请日：1990-08-13
申请人： Manabu Imahashi , Hironori Kamiya
发明人： Manabu Imahashi , Hironori Kamiya
IPC分类号： H01L29/74
CPC分类号： H01L29/7436
摘要： A lateral thyristor is provided which includes a semiconductor substrate of a first conductivity type, an epitaxial layer of a second conductivity type formed on the semiconductor substrate, an anode diffusion layer of the first conductivity type formed in the epitaxial layer, a gate diffusion layer of the first conductivity type formed in the epitaxial layer, and a buried layer of the second conductivity type formed below the anode diffusion layer and extending between the semiconductor substrate and the epitaxial layer, wherein there is a region directly below the anode diffusion layer where the anode diffusion layer and the buried layer do not overlap each other, when the lateral thyristor is looked down upon in a direction perpendicular to the principal surface of the semiconductor substrate.
摘要翻译：提供一种横向晶闸管，其包括第一导电类型的半导体衬底，形成在半导体衬底上的第二导电类型的外延层，形成在外延层中的第一导电类型的阳极扩散层，栅极扩散层在外延层中形成的第一导电类型和形成在阳极扩散层下方并在半导体衬底和外延层之间延伸的第二导电类型的掩埋层，其中在阳极扩散层的正下方存在阳极，阳极扩散层的阳极当横向晶闸管在垂直于半导体衬底的主表面的方向上向下俯视时，扩散层和掩埋层彼此不重叠。

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