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1. 发明授权

US4970686A Semiconductor memory cells and semiconductor memory device employing the semiconductor memory cells 失效
标题翻译：采用半导体存储单元的半导体存储单元和半导体存储器件
公开(公告)号：US4970686A
公开(公告)日：1990-11-13
申请号：US396246
申请日：1989-08-21
申请人： Yasuo Naruke , Thoru Mochizuki , Taira Iwase , Masamichi Asano
发明人： Yasuo Naruke , Thoru Mochizuki , Taira Iwase , Masamichi Asano
IPC分类号： G11C17/00 , G11C17/12 , G11C17/14 , G11C29/00 , G11C29/04
CPC分类号： G11C29/785 , G11C17/12
摘要： A spare memory cell comprises a read FET (Field Effect Transistor), a fusing FET and a current fuse. The FETs are connected in series between a read data line and a low voltage source. The fuse is inserted between a series node of the FETs and a write data line. The fuse is molten when data is written to the spare memory cell. By applying a power source voltage to a control electrode of the fusing FET and by applying a voltage that is higher than the power source voltage to the write data line, the fusing FET is set to its secondary breakdown state. Under this state, a large current flows through the fusing FET to cut off the fuse, thus writing data to the spare memory cell.

2. 发明授权

US5172337A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5172337A
公开(公告)日：1992-12-15
申请号：US778064
申请日：1991-12-06
申请人： Taira Iwase , Yasuo Naruke
发明人： Taira Iwase , Yasuo Naruke
IPC分类号： G11C17/14 , G11C17/16 , H01L21/82 , H01L27/10
CPC分类号： G11C17/16
摘要： A semiconductor memory device of the present invention is a semiconductor memory device formed on a semiconductor layer (30) of a first conductivity type and having a plurality of fuse melting type non-volatile memory cells (1) disposed generally in a matrix form, wherein the memory cell (1) has a read transistor (3), a current-melting fuse (7), and a fuse blow transistor (5), one end of the read transistor (3) is connected to a read data line (13), the other end thereof is connected via the current-melting fuse (7) to a write data line (17), an interconnection (C.sub.1) between the read transistor (3) and the fuse (7) is connected via the fuse blow transistor (5) to ground by a ground wiring (15), the write data lines (17) and the ground wirings (15) of the memory cells (1) disposed in a row direction are connected in common, and a noise absorbing element (21) is connected between the write data line (17) and the ground wiring (15), the noise absorbing element (21) suppressing a potential difference between the write data line (17) and the ground wiring (15) from becoming large.
摘要翻译： PCT No.PCT / JP91 / 00459 Sec。 371 1991年12月6日第 102（e）1991年12月6日授权PCT 1991年4月6日PCT。本发明的半导体存储器件是形成在第一导电类型的半导体层（30）上并具有多个保险丝熔融型非易失性存储单元（1），其通常以矩阵形式布置，其中所述存储单元（1）具有读取晶体管（3），电流熔断熔丝（7）和熔丝熔断晶体管（5）读取晶体管（3）的一端连接到读取数据线（13），其另一端通过电流熔断熔丝（7）连接到写入数据线（17），互连（C1）读取晶体管（3）和熔丝（7）经由熔丝熔断晶体管（5）通过接地布线（15），存储单元的写入数据线（17）和接地布线（15）连接到地在行方向上配置的（1）共同连接，并且在写入数据线（17）和接地布线（15）之间连接有噪声吸收元件（21），噪声抑制写入数据线（17）和接地布线（15）之间的电位差的吸收元件（21）变大。

3. 发明授权

US06529438B1 Semiconductor memory device implemented with a test circuit 失效
标题翻译：用测试电路实现的半导体存储器件
公开(公告)号：US06529438B1
公开(公告)日：2003-03-04
申请号：US09722195
申请日：2000-11-22
申请人： Yoichi Suzuki , Akihiro Mishima , Mitsuhiko Kosakai , Makoto Segawa , Yasuo Naruke
发明人： Yoichi Suzuki , Akihiro Mishima , Mitsuhiko Kosakai , Makoto Segawa , Yasuo Naruke
IPC分类号： G11C800
CPC分类号： G11C8/10 , G11C29/02
摘要： An improved semiconductor memory device capable of easily detecting the location of a defective bit line and a defective memory cell as a leakage current path for a short time is provided. A region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first large region and a remaining second large region, either of said first and second large regions being selected by simultaneously selecting a predetermined number of said column selection lines. Then, a region flowing a leakage current no smaller than a predetermined value is determined by detecting one of a first small region and a remaining second small region, said first and second small regions constituting said one of the first and second large regions, either of said first and second small regions being selected by simultaneously selecting a predetermined number of said column selection lines. For this purpose, an address signal output control circuit is provided within the semiconductor memory device. The address signal output control circuit is supplied with an address output control signal as externally given as a control signal for the purpose of selecting said row selection line by taking control of said row addressing signal in order to perform the control process as described above.
摘要翻译：提供一种改进的半导体存储器件，其能够容易地将缺陷位线和缺陷存储器单元的位置检测为短时间的漏电流路径。通过检测第一大区域和剩余第二大区域中的一个来确定流过不小于预定值的漏电流的区域，通过同时选择预定数量的所述列选择线来选择所述第一和第二大区域中的任一个。然后，通过检测构成第一和第二大区域中的一个的第一和第二小区域的第一小区域和第二小区域中的一个来确定流过不小于预定值的漏电流的区域，通过同时选择预定数量的所述列选择线来选择所述第一和第二小区域。为此，在半导体存储器件内提供地址信号输出控制电路。为了通过控制所述行寻址信号来选择所述行选择线，为了执行如上所述的控制处理，地址信号输出控制电路被提供作为外部给定的地址输出控制信号作为控制信号。

4. 发明授权

US6013931A Semiconductor device and method for producing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US6013931A
公开(公告)日：2000-01-11
申请号：US46657
申请日：1998-03-24
申请人： Wataru Igarashi , Yasuo Naruke
发明人： Wataru Igarashi , Yasuo Naruke
IPC分类号： H01L21/768 , H01L27/088 , H01L29/76
CPC分类号： H01L21/76895 , H01L27/088
摘要： A semiconductor device comprises: a semiconductor substrate; a field oxide film formed in the semiconductor substrate, the field oxide film having element forming regions on both sides thereof; a pair of MOS transistors formed in the element forming regions on both sides of the field oxide film, each of the transistors having a gate oxide film, a gate electrode and a pair of source/drain regions; an interlayer insulating film covering the semiconductor substrate, the field oxide film and the transistors; a local interconnect formed by embedding a conductive material in a first opening formed in the interlayer insulating film, the first opening being arranged above the field oxide film and having a greater width than the field oxide film, an inner one of the pair of source/drain regions of each of the pair of transistors being exposed to the first opening, the inner one of the pair of source/drain regions of one of the pair of transistors being electrically connected to the inner one of the pair of source/drain regions of the other of the pair of transistors by means of the local interconnect; and a pair of buried contacts formed by embedding a pair of conductive materials in a pair of second openings formed in the interlayer insulating film, the pair of second openings being arranged above an outer one of the pair of source/drain regions of each of the pair of transistors, the outer one of the pair of source/drain regions being exposed to the second openings.
摘要翻译：半导体器件包括：半导体衬底; 形成在所述半导体衬底中的场氧化物膜，所述场氧化物膜在其两侧具有元件形成区域; 形成在场氧化膜两侧的元件形成区域中的一对MOS晶体管，每个晶体管具有栅极氧化膜，栅极电极和一对源极/漏极区域; 覆盖半导体衬底的层间绝缘膜，场氧化物膜和晶体管; 通过在形成于所述层间绝缘膜中的第一开口中嵌入导电材料形成的局部互连，所述第一开口设置在所述场氧化膜的上方，并且具有比所述场氧化膜更大的宽度，所述一对源极/ 一对晶体管中的每一个的漏极区域暴露于第一开口，该对晶体管中的一个晶体管的一对源/漏区的一个内部一个电连接到一对源极/漏极区的内部区域一对晶体管中的另一个通过局部互连; 以及一对埋入触点，其通过将一对导电材料嵌入形成在所述层间绝缘膜中的一对第二开口中而形成，所述一对第二开口布置在所述一对第二开口中的每一个的一个源/漏区域的外侧一对晶体管，一对源极/漏极区域中的外部一个暴露于第二个开口。

5. 发明授权

US06190953B1 Semiconductor device and method for producing same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06190953B1
公开(公告)日：2001-02-20
申请号：US09438767
申请日：1999-11-12
申请人： Wataru Igarashi , Yasuo Naruke
发明人： Wataru Igarashi , Yasuo Naruke
IPC分类号： H01L21336
CPC分类号： H01L21/76895 , H01L27/088
摘要： A semiconductor device comprises: a semiconductor substrate; a field oxide film formed in the semiconductor substrate, the field oxide film having element forming regions on both sides thereof; a pair of MOS transistors formed in the element forming regions on both sides of the field oxide film, each of the transistors having a gate oxide film, a gate electrode and a pair of source/drain regions; an interlayer insulating film covering the semiconductor substrate, the field oxide film and the transistors; a local interconnect formed by embedding a conductive material in a first opening formed in the interlayer insulating film, the first opening being arranged above the field oxide film and having a greater width than the field oxide film, an inner one of the pair of source/drain regions of each of the pair of transistors being exposed to the first opening, the inner one of the pair of source/drain regions of one of the pair of transistors being electrically connected to the inner one of the pair of source/drain regions of the other of the pair of transistors by means of the local interconnect; and a pair of buried contacts formed by embedding a pair of conductive materials in a pair of second openings formed in the interlayer insulating film, the pair of second openings being arranged above an outer one of the pair of source/drain regions of each of the pair of transistors, the outer one of the pair of source/drain regions being exposed to the second openings.
摘要翻译：半导体器件包括：半导体衬底; 形成在所述半导体衬底中的场氧化物膜，所述场氧化物膜在其两侧具有元件形成区域; 形成在场氧化膜两侧的元件形成区域中的一对MOS晶体管，每个晶体管具有栅极氧化膜，栅极电极和一对源极/漏极区域; 覆盖半导体衬底的层间绝缘膜，场氧化物膜和晶体管; 通过在形成于所述层间绝缘膜中的第一开口中嵌入导电材料形成的局部互连，所述第一开口设置在所述场氧化膜的上方，并且具有比所述场氧化膜更大的宽度，所述一对源极/ 一对晶体管中的每一个的漏极区域暴露于第一开口，该对晶体管中的一个晶体管的一对源/漏区的一个内部一个电连接到一对源极/漏极区的内部区域一对晶体管中的另一个通过局部互连; 以及一对埋入触点，其通过将一对导电材料嵌入形成在所述层间绝缘膜中的一对第二开口中而形成，所述一对第二开口布置在所述一对第二开口中的每一个的一个源/漏区域的外侧一对晶体管，一对源极/漏极区域中的外部一个暴露于第二个开口。

6. 发明授权

US5002896A Mask-ROM manufacturing method that enhances integration density 失效
标题翻译： Mask-ROM制造方法，增强集成密度
公开(公告)号：US5002896A
公开(公告)日：1991-03-26
申请号：US567797
申请日：1990-08-15
申请人： Yasuo Naruke
发明人： Yasuo Naruke
IPC分类号： H01L27/112 , H01L21/033 , H01L21/225 , H01L21/28 , H01L21/8246
CPC分类号： H01L27/1126 , H01L21/033 , H01L21/2254 , H01L21/28273
摘要： A manufacturing method of a mask-ROM of two-layered gate electrode structure is provided. With this method, a cell transistor having a first-layered gate is converted into the depletion type according to data to be stored in the following manner. That is, a first conductive layer is insulatively formed over a semiconductor substrate of a first conductivity type, a silicon nitride film is formed on the first conductive layer, a polysilicon film is formed on the silicon nitride film, the polysilicon film is patterned and then altered into a silicon oxide film so as to increase its volume, and the silicon nitride film is patterned with the silicon oxide film used as a mask to form windows for permitting impurity to be doped therethrough. Then, impurity for converting cell transistors into the depletion type according to data to be stored is doped from the windows into the substrate through the first conductive layer.

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