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1. 发明授权

US06690073B2 Semiconductor integrated circuit making use of standard cells 有权
标题翻译：半导体集成电路利用标准单元
公开(公告)号：US06690073B2
公开(公告)日：2004-02-10
申请号：US09819532
申请日：2001-03-27
申请人： Yasunobu Umemoto , Toshikazu Sei , Toshiki Morimoto , Hiroaki Suzuki
发明人： Yasunobu Umemoto , Toshikazu Sei , Toshiki Morimoto , Hiroaki Suzuki
IPC分类号： H01L2976
CPC分类号： H01L27/11807 , H01L27/0211
摘要： A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.
摘要翻译：描述了能够以更高的封装密度和小尺寸的标准电池结构制造的半导体集成电路。在半导体集成电路中，衬底区域和源极区域被相邻标准单元以及位于分别从衬底区域的中心向内位移的公共接触区域共享。

2. 发明授权

US06885071B2 Semiconductor integrated circuit making use of standard cells 失效
标题翻译：半导体集成电路利用标准单元
公开(公告)号：US06885071B2
公开(公告)日：2005-04-26
申请号：US10688083
申请日：2003-10-16
申请人： Yasunobu Umemoto , Toshikazu Sei , Toshiki Morimoto , Hiroaki Suzuki
发明人： Yasunobu Umemoto , Toshikazu Sei , Toshiki Morimoto , Hiroaki Suzuki
IPC分类号： H01L21/822 , H01L21/82 , H01L21/8238 , H01L27/02 , H01L27/04 , H01L27/092 , H01L27/118 , H01L29/76
CPC分类号： H01L27/11807 , H01L27/0211
摘要： A semiconductor integrated circuit which is capable of being manufactured with a higher packing density and a small-size structure of standard cells is described. In the semiconductor integrated circuit, substrate regions and source regions are shared by adjacent standard cells as well as common contact regions which are located inward displaced respectively from the centers of the substrate regions.
摘要翻译：描述了能够以更高的封装密度和小尺寸的标准电池结构制造的半导体集成电路。在半导体集成电路中，衬底区域和源极区域被相邻标准单元以及位于分别从衬底区域的中心向内位移的公共接触区域共享。

3. 发明授权

US5614842A Semiconductor integrated circuit with buffer circuit and manufacturing method thereof 失效
标题翻译：具有缓冲电路的半导体集成电路及其制造方法
公开(公告)号：US5614842A
公开(公告)日：1997-03-25
申请号：US522962
申请日：1995-09-01
申请人： Katsuro Doke , Toshikazu Sei , Yasunobu Umemoto , Eiji Ban
发明人： Katsuro Doke , Toshikazu Sei , Yasunobu Umemoto , Eiji Ban
IPC分类号： H03K19/0175 , H03K19/00 , H03K19/0948
CPC分类号： H03K19/0013
摘要： A semiconductor integrated circuit with a buffer circuit is disclosed. The source of the first P(N)MOS transistor is connected to a voltage supply (ground), its drain being connected to an output terminal. The source of the first N(P)MOS transistor is connected to the ground (voltage supply), its drain being connected to the output terminal. The gate of the second P(N)MOS transistor is connected to the gate of the first NMOS transistor, its source being connected to the voltage supply (ground) and its drain being connected to the output terminal. The gate of the second N(P)MOS transistor is connected to the gate of the first PMOS transistor, at least one of its source and drain being floated. A controller responses to an enable signal and an input signal to apply control signals to the gates of the first PMOS and NMOS transistors. By these control signals, any one of the first PMOS and NMOS transistors is turned on based on the input signal level when the enable signal is on. Whereas both the first PMOS and NMOS transistors are turned off irrespective of the input signal level when the enable signal is off. The semiconductor integrated circuit further includes an input buffer connected the output terminal via a resistor. The input buffer applies a signal appearing at the output terminal to internal circuitry of the semiconductor integrated circuit.
摘要翻译：公开了一种具有缓冲电路的半导体集成电路。第一P（N）MOS晶体管的源极连接到电压源（地），其漏极连接到输出端子。第一N（P）MOS晶体管的源极连接到地（电源），其漏极连接到输出端。第二P（N）MOS晶体管的栅极连接到第一NMOS晶体管的栅极，其源极连接到电压源（地），其漏极连接到输出端子。第二N（P）MOS晶体管的栅极连接到第一PMOS晶体管的栅极，其源极和漏极中的至少一个浮动。控制器响应于使能信号和输入信号，以将控制信号施加到第一PMOS和NMOS晶体管的栅极。通过这些控制信号，当使能信号为接通时，基于输入信号电平，第一PMOS和NMOS晶体管中的任何一个导通。尽管当使能信号关闭时，第一PMOS晶体管和NMOS晶体管都被切断，而与输入信号电平无关。半导体集成电路还包括经由电阻器连接输出端子的输入缓冲器。输入缓冲器将出现在输出端子处的信号施加到半导体集成电路的内部电路。

4. 发明授权

US06271548B1 Master slice LSI and layout method for the same 失效
标题翻译：主片LSI和布局方法相同
公开(公告)号：US06271548B1
公开(公告)日：2001-08-07
申请号：US08859108
申请日：1997-05-20
申请人： Yasunobu Umemoto , Yukinori Uchino , Toshikazu Sei , Muneaki Maeno
发明人： Yasunobu Umemoto , Yukinori Uchino , Toshikazu Sei , Muneaki Maeno
IPC分类号： H01L2710
CPC分类号： H01L27/11803 , H01L2924/0002 , H01L2924/00
摘要： A master slice layout technology is provided to improve integration density of a semiconductor integrated circuit such as ASIC. In particular, a plurality of gate basic cells are arranged on a semiconductor chip and then a wiring channel grid having non-uniform pitches is defined on the gate basic cells. If a layout of metal wirings is designed along the wiring channel grid, miniaturizable patterns can be set to smaller values while maintaining line widths of predetermined metal wirings such as power supply wirings at preselected values. Since flexibility for the layout of the metal wiring layers is large, miniaturization of the patterns can be attained even if design rules for basic cell process and wiring process are different.
摘要翻译：提供了主切片布局技术来提高诸如ASIC之类的半导体集成电路的集成密度。具体而言，在半导体芯片上配置有多个栅极基体单元，在栅极基体单元上形成具有不均匀间距的布线沟道栅格。如果沿着布线通道格栅设计金属布线的布局，则可以将小型化图案设置为较小的值，同时保持预定金属布线（例如预选值的电源布线）的线宽。由于金属布线层的布局的灵活性大，即使基本单元处理和布线处理的设计规则不同，也可以实现图案的小型化。

5. 发明授权

US6093942A Semiconductor device with improved pad layout 失效
标题翻译：具有改善焊盘布局的半导体器件
公开(公告)号：US6093942A
公开(公告)日：2000-07-25
申请号：US305472
申请日：1999-05-06
申请人： Toshikazu Sei , Yasunobu Umemoto
发明人： Toshikazu Sei , Yasunobu Umemoto
IPC分类号： H01L21/60 , H01L23/485 , H01L27/118
CPC分类号： H01L24/06 , H01L2224/05553 , H01L2224/05554 , H01L2224/05624 , H01L2924/01004 , H01L2924/01013 , H01L2924/01033 , H01L2924/14 , H01L2924/1433
摘要： First I/O signal pads are arranged along the periphery of a semiconductor chip except corner sections thereof at a first pitch, and second I/O signal pads and power supply pads are arranged in the corner sections of the semiconductor chip. In this case, the second I/O signal pads and the power supply pads are alternately arranged at the first pitch, and arrangement of the power supply pads are set so that the pads are located at fixed sites common to semiconductor chips. With this arrangement, the second I/O signal pads are arranged at a pitch wider than the first pitch.
摘要翻译：第一I / O信号焊盘沿着半导体芯片的外围以除了其第一节距的角部分布置，并且第二I / O信号焊盘和电源焊盘布置在半导体芯片的拐角部分中。在这种情况下，第二I / O信号焊盘和电源焊盘以第一间距交替布置，并且电源焊盘的布置被设置为使得焊盘位于半导体芯片共同的固定位置。利用这种布置，第二I / O信号焊盘以比第一间距更宽的间距布置。

6. 发明授权

US6075389A Operation speed measuring circuit and semiconductor device incorporating the same circuit 失效
标题翻译：运行速度测量电路和包含相同电路的半导体器件
公开(公告)号：US6075389A
公开(公告)日：2000-06-13
申请号：US522955
申请日：1995-09-01
申请人： Yasunobu Umemoto , Toshikazu Sei , Katsuro Doke , Eiji Ban
发明人： Yasunobu Umemoto , Toshikazu Sei , Katsuro Doke , Eiji Ban
IPC分类号： G01R31/28 , G01R31/30 , H01L21/66 , H01L21/82 , H01L21/822 , H01L27/04 , H03K5/13 , H03D3/00
CPC分类号： G01R31/3016 , H03K5/133
摘要： An operation speed measuring circuit measures a difference in propagation delay time between first and second path 2, 3 including logic gates connected in series and thus confirms that an element provided on a chip obtains a specified operation speed. This operation speed measuring circuit is so constructed as to be controllable by an input signal IN from one input terminal 1 and can be therefore disposed in such an area that the number of placeable terminals is restricted down to a small number. When this operation speed measuring circuit is provided with a power supply terminal independent of other circuits, constructions of other circuits can be independently designed. When the operation speed measuring circuit is disposed in the area independent of an intra-chip integrated circuit design area, a degree of freedom of designing other circuits is improved. This independent area is set in one of corner areas on the semiconductor chip that have hitherto been nothing but empty areas, the degree of freedom of designing the circuit is further improved.
摘要翻译：操作速度测量电路测量包括串联连接的逻辑门的第一和第二路径2,3之间的传播延迟时间差，从而确认芯片上提供的元件获得指定的操作速度。该操作速度测量电路被构造成可以通过来自一个输入端子1的输入信号IN来控制，并且因此能够被设置在可放置端子的数量被限制在少数的区域内。当该操作速度测量电路具有独立于其它电路的电源端子时，可独立地设计其它电路的结构。当操作速度测量电路被设置在与片内集成电路设计区域无关的区域中时，提高了设计其他电路的自由度。这个独立区域被设置在半导体芯片的一个角区域中，迄今为止只是空白区域，电路设计的自由度进一步提高。

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