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1. 发明授权

US06999788B2 Radio transmitter that determines proper standard 失效
标题翻译：确定适当标准的无线电发射机
公开(公告)号：US06999788B2
公开(公告)日：2006-02-14
申请号：US10290257
申请日：2002-11-08
申请人： Yasuhiro Takeda , Masashi Naito
发明人： Yasuhiro Takeda , Masashi Naito
IPC分类号： H04B1/02 , H04B7/212 , H01Q11/12 , H04M3/00 , H04J3/00
CPC分类号： H04B1/38
摘要： A radio transmitter includes a CPU, functioning to allow the radio signal to be transmitted in event of a decision result that the radio signal transmission should be permitted but, in event of a decision result that the radio signal transmission should not be permitted, functions to allow the radio signal to be stopped and to instruct the alarm output section to output an abnormal alarm; a distributor, functioning to distribute a radio signal outputted from the radio transmitter to the outside; a transmitter; a spectral analysis, functioning to perform a frequency analysis of the radio signal according to the standard information; a power comparator section, to decide whether or not a transmission of the radio signal should be permitted by comparing the result of the frequency analysis with the standard information; and an alarm output section.
摘要翻译：无线电发射机包括CPU，其功能是允许在确定无线电信号传输应允许的判定结果的情况下发送无线电信号，但是在无法允许无线电信号传输的判定结果的情况下，允许无线电信号停止，并指示报警输出部分输出异常报警; 分配器，用于将从无线电发射机输出的无线电信号分配到外部; 发射机; 频谱分析，用于根据标准信息执行无线电信号的频率分析; 功率比较器部，用于通过将频率分析的结果与标准信息进行比较来判定是否应允许无线电信号的发送; 和报警输出部分。

2. 发明授权

US08467471B2 Coding and modulation selecting method and wireless communication equipment 失效
标题翻译：编码和调制选择方法及无线通信设备
公开(公告)号：US08467471B2
公开(公告)日：2013-06-18
申请号：US12554145
申请日：2009-09-04
申请人： Takashi Yano , Masashi Naito , Takehiko Kobayashi
发明人： Takashi Yano , Masashi Naito , Takehiko Kobayashi
IPC分类号： H04L27/00
CPC分类号： H04L1/0026 , H04L1/0016 , H04L1/0021 , H04L1/1845
摘要： Disclosed herewith is a radio communication apparatus capable of selecting proper one of plural communication modes such as a MIMO communication system so as to obtain a higher communication rate within a range in which chain retransmission occurrence is prevented. The MIMO system deciding section of the transmitter unit decides a proper MIMO system with reference to the CQI value demultiplexed by a demultiplexer and the AMC table controlling section changes the MCS value step by step according to the transmission count and the result (success/failure) of the communication. Furthermore, the AMC table controlling section updates the mean rate in the measured rate table when the subject data is received successfully or when the transmission count reaches the maximum value.
摘要翻译：这里公开了一种无线电通信装置，其能够选择诸如MIMO通信系统的多种通信模式中的适当一种，以便在防止链路重发发生的范围内获得更高的通信速率。发射机单元的MIMO系统判定部分参照由解复用器解复用的CQI值决定适当的MIMO系统，并且AMC表控制部分根据传输计数和结果（成功/失败）逐步改变MCS值，的沟通。此外，当成功接收到被摄体数据或发送计数达到最大值时，AMC表控制部分更新测量速率表中的平均速率。

3. 发明授权

US07721165B2 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：US07721165B2
公开(公告)日：2010-05-18
申请号：US11599388
申请日：2006-11-15
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译：一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统，对连续扇区数据的读命令作出响应。

4. 发明授权

US06888393B2 Amplitude limiting apparatus and multi-carrier signal generating apparatus 失效
标题翻译：振幅限制装置和多载波信号发生装置
公开(公告)号：US06888393B2
公开(公告)日：2005-05-03
申请号：US10631889
申请日：2003-08-01
申请人： Masashi Naito
发明人： Masashi Naito
IPC分类号： H03G11/00 , H04L27/26 , H03L5/00
CPC分类号： H03G11/008 , H04L27/2624
摘要： A peak level of amplitude of transmission signals in a multi-carrier communication system or the like is to be effectively suppressed. A transmission data generating unit generates digital transmission data from original data by an OFDM system. A limiter of a peak suppressing unit limits a level of transmission data using thresholds. A subtractor subtracts output data of the limiter from the transmission data to generate differential data. A subtractor suppresses the peak level by subtracting the differential data from transmission data whose timing is coordinated by delay units. A transmitter unit converts the transmission data whose peak level is suppressed into analog transmission signals, further converts their frequency, amplifies their power, and transmits the frequency-converted and power-amplified signals to a radio line via an antenna.
摘要翻译：为了有效地抑制多载波通信系统等中的发送信号的振幅的峰值电平。发送数据生成单元通过OFDM系统从原始数据生成数字发送数据。峰值抑制单元的限制器使用阈值限制传输数据的级别。减法器从发送数据中减去限幅器的输出数据，生成差分数据。减法器通过从通过延迟单元协调定时的发送数据中减去差分数据来抑制峰值电平。发射机单元将其峰值电平被抑制的传输数据转换为模拟传输信号，进一步转换其频率，放大其功率，并经由天线将频率转换和功率放大的信号发射到无线电线路。

5. 发明授权

US06662002B2 Frequency conversion circuit and transmitter 失效
公开(公告)号：US06662002B2
公开(公告)日：2003-12-09
申请号：US09683393
申请日：2001-12-21
申请人： Mitsuo Kubo , Masashi Naito
发明人： Mitsuo Kubo , Masashi Naito
IPC分类号： H04B116
CPC分类号： H04B1/04 , H04B2001/0491
摘要： A frequency conversion circuit for changing a frequency of an input signal to obtain an output signal, includes: a sum holding unit holding a sum; an integrating unit updating the sum by changing the sum by a natural number a in one direction at each input of a first predetermined signal based on the input signal; and an output signal generating unit outputting a second predetermined signal as the output signal at each time at which the sum has gone over (b*N+c), where N is an integer, c is a constant integer and b is a natural number equal to or larger than a.

6. 发明授权

US06199187B1 External storage device and memory access control method thereof 有权
公开(公告)号：US06199187B1
公开(公告)日：2001-03-06
申请号：US09544609
申请日：2000-04-06
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： H03M1300
CPC分类号： G06F11/1008
摘要： High speed memory access and transparent error detection and correction using a single error correcting means are obtained. A host computer writes (2N−1)th (odd-numbered) sector data in one of the first memory and second memory (e.g., constituted by one or more memories) and 2N−th (even-numbered) sector data in the other of the first and second memory. Accordingly, (2N−1)th sector data can be read out from one of the first memory and second memory to the host computer, and at the same time (i.e., simultaneously), 2N−th sector data (i.e., next sector data to be read by the host computer) can be read out from the other of the first memory and second memory and error detection and correction can be performed in the error correcting means. Also, during a next cycle, the 2N−th (even-numbered) sector data read out from one of the first memory and second memory can be outputted to the host computer, and at the same time (i.e., simultaneously), error detection and error correction of the (2N+1)th sector data (next sector data to be read by the host computer) read out from one of the first computer and second computer can be performed in the error correcting means. Consequently, the host computer always reads sector data, and at the same time, error detection and the error correction for a next sector data are simultaneously performed thereby the time required for error detection and error correction can be reduced apparently (i.e., made transparent to the host computer 2) and memory access can be obtained.

7. 再颁专利

USRE45857E1 External storage device and memory access control method thereof 有权
标题翻译：外部存储装置及其存储器访问控制方法
公开(公告)号：USRE45857E1
公开(公告)日：2016-01-19
申请号：US13475679
申请日：2012-05-18
申请人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
发明人： Takayuki Tamura , Shigemasa Shiota , Kunihiro Katayama , Masashi Naito
IPC分类号： G11C29/00 , G06F11/10
CPC分类号： G06F11/1008
摘要： A storage device, including: a non-volatile semiconductor memory which is electrically erasable; a system interface coupled with an external host system; and a controller reading data from the non-volatile semiconductor memory and transmitting data to the host system via the system interface in response to a read command received by the system interface from the host system; and wherein the controller starts reading (N+n)th sector data from the non-volatile semiconductor memory, while the controller transmits Nth sector data that has been read from the non-volatile semiconductor memory to the host system via the system interface, in response to the read command for successive sector data.
摘要翻译：一种存储装置，包括：电可擦除的非易失性半导体存储器; 与外部主机系统耦合的系统接口; 以及控制器，从所述非易失性半导体存储器读取数据，并且响应于所述系统接口从所述主机系统接收到的读取命令，经由所述系统接口向所述主机系统发送数据; 并且其中所述控制器从所述非易失性半导体存储器开始读取第（N + n）个扇区数据，同时所述控制器经由所述系统接口将从所述非易失性半导体存储器读取的第N个扇区数据发送到所述主机系统，对连续扇区数据的读命令作出响应。

8. 发明授权

US08064257B2 Semiconductor memory device having faulty cells 有权
标题翻译：具有故障单元的半导体存储器件
公开(公告)号：US08064257B2
公开(公告)日：2011-11-22
申请号：US12615502
申请日：2009-11-10
申请人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
发明人： Kunihiro Katayama , Takayuki Tamura , Satoshi Watatani , Kiyoshi Inoue , Shigemasa Shiota , Masashi Naito
IPC分类号： G11C11/34
CPC分类号： G11C16/349 , G11C29/76 , G11C29/88
摘要： In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.
摘要翻译：响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作。所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

9. 发明申请

US20090060073A1 METHOD FOR SUPPRESSING PEAK POWER OF ORTHOGONALLY MULTIPLEXED SIGNAL, PEAK POWER SUPPRESSING CIRCUIT, AND TRANSMITTER 有权
标题翻译：用于抑制正交多路信号峰值功率的方法，峰值功率抑制电路和发射机
公开(公告)号：US20090060073A1
公开(公告)日：2009-03-05
申请号：US12199595
申请日：2008-08-27
申请人： Takashi Yano , Shigenori Hayase , Masashi Naito
发明人： Takashi Yano , Shigenori Hayase , Masashi Naito
IPC分类号： H04J11/00
CPC分类号： H04L27/2614 , H04L27/2618 , H04L27/2623 , H04L27/2624
摘要： To suppress the peak of the orthogonal multiplex transmission signal which is small in deterioration of the quality of the reception signal by generating the cancellation waveform in synchronization with the timing of the symbol of the transmission signal. There is provided a peak suppressing method that suppresses peaks of an orthogonally multiplexed signal whose orthogonality is ensured in given time units, the method comprising: a first step of detecting the peaks of the orthogonally multiplexed signal; a second step of generating a peak cancellation waveform based on the detected peaks of the orthogonally multiplexed signal; and a third step of removing the peak of the orthogonally multiplexed signal from the orthogonally multiplexed signal using the generated peak cancellation waveform. The second step comprises generating the peak cancellation waveform in said time units of the orthogonally multiplexed signal.
摘要翻译：通过与发送信号的符号的定时同步地生成消除波形来抑制接收信号的质量恶化的正交多路传输信号的峰值。提供一种峰值抑制方法，其抑制以给定时间单位确保正交性的正交复用信号的峰值，该方法包括：检测正交多路复用信号的峰值的第一步骤; 基于检测到的正交多路复用信号的峰值产生峰值消除波形的第二步骤; 以及使用所生成的峰值抵消波形从正交多路复用信号中除去正交多路复用信号的峰值的第三步骤。第二步包括以正交复用信号的所述时间单位产生峰值消除波形。

10. 发明授权

US07042935B2 Equalizer and equalization method 失效
标题翻译：均衡器和均衡方法
公开(公告)号：US07042935B2
公开(公告)日：2006-05-09
申请号：US10011273
申请日：2001-12-11
申请人： Nobuaki Kawahara , Masashi Naito
发明人： Nobuaki Kawahara , Masashi Naito
IPC分类号： H03H7/30
CPC分类号： H04L25/03114 , H04L7/04 , H04L2025/0342 , H04L2025/0377
摘要： An equalizer and an equalization method capable of suppressing distortion specific to radio unit and reducing both the oversampling number and the amount of calculations without causing characteristic deterioration. The equalizer, which equalizes a received signal with periodically inserted known pilot symbols, includes a synchronization processing section that detects symbol synchronization points using pilot symbols included in the received signal, a plurality of equalization factor calculation sections which use the symbol synchronization points and points shifted in time before and after the symbol synchronization point as symbol synchronization point candidates, and calculate equalization factors for the respective symbol synchronization point candidates, and an optimization/equalization processing section which selects an optimal symbol synchronization point and corresponding optimal equalization factor from among a plurality of symbol synchronization point candidates and corresponding equalization factors, and equalizes the received signal using the optimal equalization factor.
摘要翻译：一种均衡器和均衡方法，其能够抑制无线电单元特有的失真并减少过采样数量和计算量而不引起特性劣化。使用周期性插入的已知导频符号来均衡接收信号的均衡器包括使用包括在接收信号中的导频符号来检测符号同步点的同步处理部分，使用符号同步点和偏移点的多个均衡因子计算部分在符号同步点之前和之后的时间作为符号同步点候选，并计算各个符号同步点候选的均衡因子，以及优化/均衡处理部，其从多个中选择最佳符号同步点和对应的最优均衡因子的符号同步点候选和相应的均衡因子，并且使用最优均衡因子来均衡接收信号。

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