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1. 发明授权

US07112833B2 Semiconductor device and manufacturing method thereof 失效
公开(公告)号：US07112833B2
公开(公告)日：2006-09-26
申请号：US10788278
申请日：2004-03-01
申请人： Yasuhiro Shimamoto , Shinichi Saito , Shimpei Tsujikawa
发明人： Yasuhiro Shimamoto , Shinichi Saito , Shimpei Tsujikawa
IPC分类号： H01L29/76 , H01L21/336
CPC分类号： H01L21/28202 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659
摘要： The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at the interface between a semiconductor substrate and an alumina film. By so doing, a gate insulator composed of the silicon oxynitride film and the alumina film is constituted. The silicon oxynitride film is formed by performing a thermal treatment of a silicon oxide film formed on the semiconductor substrate in a NO or N2O atmosphere. In this manner, the fixed charges in the silicon oxynitride film are set to 5×1012 cm−2 or less, and the fixed charges in the interface between the silicon oxynitride film and the alumina film are set to 5×1012 cm−2 or more.

2. 发明申请

US20060273357A1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060273357A1
公开(公告)日：2006-12-07
申请号：US11503935
申请日：2006-08-15
申请人： Yasuhiro Shimamoto , Shinichi Saito , Shimpei Tsujikawa
发明人： Yasuhiro Shimamoto , Shinichi Saito , Shimpei Tsujikawa
IPC分类号： H01L29/76
CPC分类号： H01L21/28202 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659
摘要： The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at the interface between a semiconductor substrate and an alumina film. By so doing, a gate insulator composed of the silicon oxynitride film and the alumina film is constituted. The silicon oxynitride film is formed by performing a thermal treatment of a silicon oxide film formed on the semiconductor substrate in a NO or N2O atmosphere. In this manner, the fixed charges in the silicon oxynitride film are set to 5×1012 cm−2 or less, and the fixed charges in the interface between the silicon oxynitride film and the alumina film are set to 5×1012 cm−2 or more.
摘要翻译：提供了能够通过抑制由于固定电荷引起的载流子散射来降低MISFET中的功耗的技术。在半导体基板和氧化铝膜之间的界面处形成物理厚度为1.5nm以上，相对介电常数为4.1以上的氮氧化硅膜。由此构成由氧氮化硅膜和氧化铝膜构成的栅极绝缘体。氮氧化硅膜是通过在NO或N 2 O气氛中进行在半导体衬底上形成的氧化硅膜的热处理而形成的。以这种方式，将氧氮化硅膜中的固定电荷设定为5×10 12 -2 -2或更小，并且在氮氧化硅膜和氧化铝膜设定为5×10 12 cm -2以上。

3. 发明授权

US07432216B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07432216B2
公开(公告)日：2008-10-07
申请号：US11503935
申请日：2006-08-15
申请人： Yasuhiro Shimamoto , Shinichi Saito , Shimpei Tsujikawa
发明人： Yasuhiro Shimamoto , Shinichi Saito , Shimpei Tsujikawa
IPC分类号： H01L21/31 , H01L21/8238 , H01L21/336 , H01L29/06
CPC分类号： H01L21/28202 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659
摘要： The technique capable of reducing the power consumption in the MISFET by suppressing the scattering of the carriers due to the fixed charges is provided. A silicon oxynitride film with a physical thickness of 1.5 nm or more and the relative dielectric constant of 4.1 or higher is formed at the interface between a semiconductor substrate and an alumina film. By so doing, a gate insulator composed of the silicon oxynitride film and the alumina film is constituted. The silicon oxynitride film is formed by performing a thermal treatment of a silicon oxide film formed on the semiconductor substrate in a NO or N2O atmosphere. In this manner, the fixed charges in the silicon oxynitride film are set to 5×1012 cm−2 or less, and the fixed charges in the interface between the silicon oxynitride film and the alumina film are set to 5×1012 cm−2 or more.
摘要翻译：提供了能够通过抑制由于固定电荷引起的载流子散射来降低MISFET中的功耗的技术。在半导体基板和氧化铝膜之间的界面处形成物理厚度为1.5nm以上，相对介电常数为4.1以上的氮氧化硅膜。由此构成由氧氮化硅膜和氧化铝膜构成的栅极绝缘体。氮氧化硅膜是通过在NO或N 2 O气氛中进行在半导体衬底上形成的氧化硅膜的热处理而形成的。以这种方式，将氧氮化硅膜中的固定电荷设定为5×10 12 -2 -2或更小，并且在氮氧化硅膜和氧化铝膜设定为5×10 12 cm -2以上。

4. 发明授权

US07863125B2 Manufacturing method of CMOS type semiconductor device, and CMOS type semiconductor device 有权
标题翻译： CMOS型半导体器件的制造方法以及CMOS型半导体器件
公开(公告)号：US07863125B2
公开(公告)日：2011-01-04
申请号：US12492648
申请日：2009-06-26
申请人： Shimpei Tsujikawa , Yasuhiko Akamatsu , Hiroshi Umeda , Jiro Yugami , Masaharu Mizutani , Masao Inoue , Junichi Tsuchimoto , Kouji Nomura
发明人： Shimpei Tsujikawa , Yasuhiko Akamatsu , Hiroshi Umeda , Jiro Yugami , Masaharu Mizutani , Masao Inoue , Junichi Tsuchimoto , Kouji Nomura
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.
摘要翻译：在这种CMOS型半导体器件的制造方法中，能够抑制在栅极电极中含有硼的情况下，从pMOS晶体管的栅电极到半导体衬底的硼渗透，同时能够提高pMOS的NBTI寿命提供了晶体管，而不降低nMOS晶体管的性能。关于本发明的CMOS型半导体器件的制造方法具有以下工序。卤素引入pMOS晶体管形成区域的半导体衬底。接下来，在pMOS晶体管形成区域的半导体衬底上形成栅极绝缘膜。接下来，将氮引入到栅极绝缘膜。

5. 发明授权

US06982468B2 Semiconductor device and method for manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06982468B2
公开(公告)日：2006-01-03
申请号：US10942014
申请日：2004-09-16
申请人： Shimpei Tsujikawa , Toshiyuki Mine , Jiro Yugami , Natsuki Yokoyama , Tsuyoshi Yamauchi
发明人： Shimpei Tsujikawa , Toshiyuki Mine , Jiro Yugami , Natsuki Yokoyama , Tsuyoshi Yamauchi
IPC分类号： H01L29/76
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film
摘要翻译：一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时将氮气引入未被除去的二氧化硅的表面，依次溶解并且去除引入氮的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面

6. 发明授权

US09899385B2 Semiconductor integrated circuit and manufacturing method thereof 有权
公开(公告)号：US09899385B2
公开(公告)日：2018-02-20
申请号：US13480956
申请日：2012-05-25
申请人： Takashi Yamazaki , Shimpei Tsujikawa
发明人： Takashi Yamazaki , Shimpei Tsujikawa
IPC分类号： H01L29/66 , H01L27/092 , H01L21/8238 , H01L27/02
CPC分类号： H01L27/0922 , H01L21/823842 , H01L27/0266 , H01L27/0285
摘要： A semiconductor integrated circuit includes a protected circuit connected to two power supply lines that provide a supply voltage, a detecting circuit that includes a resistive element and a capacitive element connected in series between two power supply lines and detects a surge generated in the power supply line based on potential variation of an inter-element connecting node, and a protection transistor that is connected between two power supply lines and has a control electrode connected to an output of the detecting circuit. The protection transistor has the control electrode formed from a different electrode material having a work function difference from a transistor of the same channel conductivity type in the protected circuit, to have a different threshold voltage from the transistor so that the amount of leakage current per unit channel width may be smaller compared with the transistor.

7. 发明申请

US20120307410A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体集成电路及其制造方法
公开(公告)号：US20120307410A1
公开(公告)日：2012-12-06
申请号：US13480956
申请日：2012-05-25
申请人： Takashi Yamazaki , Shimpei Tsujikawa
发明人： Takashi Yamazaki , Shimpei Tsujikawa
IPC分类号： H02H3/02 , H01L21/336
CPC分类号： H01L27/0922 , H01L21/823842 , H01L27/0266 , H01L27/0285
摘要： A semiconductor integrated circuit includes a protected circuit connected to two power supply lines that provide a supply voltage, a detecting circuit that includes a resistive element and a capacitive element connected in series between two power supply lines and detects a surge generated in the power supply line based on potential variation of an inter-element connecting node, and a protection transistor that is connected between two power supply lines and has a control electrode connected to an output of the detecting circuit. The protection transistor has the control electrode formed from a different electrode material having a work function difference from a transistor of the same channel conductivity type in the protected circuit, to have a different threshold voltage from the transistor so that the amount of leakage current per unit channel width may be smaller compared with the transistor.
摘要翻译：半导体集成电路包括连接到提供电源电压的两条电源线的保护电路，包括电阻元件和串联连接在两条电源线之间的电容元件的检测电路，并且检测在电源线中产生的浪涌基于元件间连接节点的电位变化，以及连接在两个电源线之间并具有连接到检测电路的输出的控制电极的保护晶体管。保护晶体管具有由与受保护电路中的相同沟道导电类型的晶体管具有功函数差的不同电极材料形成的控制电极，以具有与晶体管不同的阈值电压，使得每单位的漏电流量通道宽度可能比晶体管更小。

8. 发明授权

US06777296B2 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06777296B2
公开(公告)日：2004-08-17
申请号：US10321501
申请日：2002-12-18
申请人： Shimpei Tsujikawa , Toshiyuki Mine , Jiro Yugami , Hirotaka Hamamura
发明人： Shimpei Tsujikawa , Toshiyuki Mine , Jiro Yugami , Hirotaka Hamamura
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/02186 , H01L21/02189 , H01L21/02274 , H01L21/02337 , H01L21/28194 , H01L21/28202 , H01L21/31604 , H01L29/517 , H01L29/518 , H01L29/66545
摘要： Disclosed is a method of improving smoothness on a surface of a gate dielectric composed of a high dielectric film made of metal oxide. A dielectric film with a high permittivity made of metal oxide such as a TiO2 film or a ZrO2 film having an amorphous structure is deposited over a silicon substrate by the plasma enhanced chemical vapor deposition method, and the film is used as a gate dielectric. Since the gate dielectric has good surface smoothness, simultaneous reductions of both the film thickness of a gate dielectric and the gate leakage current can be achieved. In addition, it is also possible to reduce the variation in the characteristics of the devices.
摘要翻译：公开了一种提高由金属氧化物构成的高电介质膜构成的栅极电介质的表面的平滑度的方法。通过等离子体增强化学气相沉积法在硅衬底上沉积具有由诸如TiO 2膜或具有无定形结构的ZrO 2膜的金属氧化物的高介电常数的介电膜，并且该膜用作栅极电介质。由于栅极电介质具有良好的表面平滑度，因此可以实现栅极电介质的膜厚度和栅极漏电流的同时减小。此外，还可以减小装置的特性的变化。

9. 发明申请

US20110031981A1 VALUATION METHOD OF DIELECTRIC BREAKDOWN LIFETIME OF GATE INSULATING FILM, VALUATION DEVICE OF DIELECTRIC BREAKDOWN LIFETIME OF GATE INSULATING FILM AND PROGRAM FOR EVALUATING DIELECTRIC BREAKDOWN LIFETIME OF GATE INSULATING FILM 审中-公开
标题翻译：栅绝缘膜电介质断裂寿命估算方法，绝缘膜绝缘断裂寿命估值装置及栅极绝缘膜电介质断裂寿命评估程序
公开(公告)号：US20110031981A1
公开(公告)日：2011-02-10
申请号：US12849096
申请日：2010-08-03
申请人： Shimpei Tsujikawa
发明人： Shimpei Tsujikawa
IPC分类号： G01R31/12
CPC分类号： G01R31/2623 , G01R31/2639 , G01R31/2642
摘要： A valuation method of a dielectric breakdown lifetime of a gate insulating film for evaluating the dielectric breakdown lifetime of the gate insulating film of a MOS type element includes the steps of: deciding a Weibull slope of lifetime distribution until reaching a soft breakdown of the gate insulating film of the MOS type element; deciding a detection condition of the soft breakdown from the decided Weibull slope after the above step; and executing a dielectric breakdown test by using the decided detection condition.
摘要翻译：用于评估MOS型元件的栅极绝缘膜的介电击穿寿命的栅极绝缘膜的绝缘击穿寿命的估值方法包括以下步骤：确定寿命分布的威布尔斜率直到达到栅极绝缘的软击穿 MOS型元件的膜; 在上述步骤之后，从决定的威布尔斜率决定软击穿的检测条件; 以及通过使用所确定的检测条件执行介电击穿测试。

10. 发明授权

US06897104B2 Semiconductor device and method for manufacturing thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06897104B2
公开(公告)日：2005-05-24
申请号：US10452126
申请日：2003-06-03
申请人： Shimpei Tsujikawa , Toshiyuki Mine , Jiro Yugami , Natsuki Yokoyama , Tsuyoshi Yamauchi
发明人： Shimpei Tsujikawa , Toshiyuki Mine , Jiro Yugami , Natsuki Yokoyama , Tsuyoshi Yamauchi
IPC分类号： H01L21/316 , H01L21/318 , H01L21/8234 , H01L27/088 , H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device and a method for manufacturing the same of forming a silicon nitride film selectively without giving damages or contaminations to a surface of the silicon substrate thereby forming different types of gate dielectrics in one identical silicon substrate, are obtained by forming a silicon dioxide on the surface of a silicon substrate, then removing a portion thereof, forming a silicon nitride film to the surface of the substrate from which the silicon dioxide has been removed and, simultaneously, introducing nitrogen to the surface of the silicon dioxide which is left not being removed or, alternatively, depositing a silicon dioxide on the surface of the silicon substrate by chemical vapor deposition, then removing a portion thereof, forming a silicon nitride film on the surface of a substrate from which the silicon dioxide has been removed, and, simultaneously, introducing nitrogen to the surface of the silicon dioxide left not being removed, successively, dissolving and removing nitrogen-introduced silicon oxide film to expose the surface of the substrate and oxidizing the exposed surface of the silicon substrate and the silicon nitride film.
摘要翻译：一种半导体器件及其制造方法，其选择性地形成氮化硅膜，而不会对硅衬底的表面造成损害或污染，从而在一个相同的硅衬底中形成不同类型的栅极电介质，通过在二氧化硅上形成二氧化硅硅衬底的表面，然后去除其一部分，在已经除去二氧化硅的衬底的表面上形成氮化硅膜，同时将氮引入二氧化硅的不是去除或者通过化学气相沉积在硅衬底的表面上沉积二氧化硅，然后去除其一部分，在去除二氧化硅的衬底的表面上形成氮化硅膜，同时将氮气引入未被除去的二氧化硅的表面，依次溶解并且移除氮导入的氧化硅膜以暴露衬底的表面并氧化硅衬底和氮化硅膜的暴露表面。

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