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1. 发明授权

US07115966B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US07115966B2
公开(公告)日：2006-10-03
申请号：US10375125
申请日：2003-02-28
申请人： Yasuhiro Ido , Kazushi Kono , Takeshi Iwamoto
发明人： Yasuhiro Ido , Kazushi Kono , Takeshi Iwamoto
IPC分类号： H01L29/00 , H01L29/73
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： On a semiconductor substrate a silicon oxide film is formed and provided with a recess. In the recess a reflector layer of copper is disposed as a blocking layer with a barrier metal posed therebetween. The reflector layer of copper is covered with a silicon oxide film and thereon a fuse region provided with a plurality of fuses is provided. The reflector layer of copper has a plane of reflection recessed downward to reflect a laser beam. The reflector layer of copper is arranged to overlap substantially the entirety of the fuse region, as seen in a plane. A laser beam radiated to blow the fuse can have a reduced effect on a vicinity of the fuse region. A semiconductor device reduced in size can be obtained.
摘要翻译：在半导体衬底上形成氧化硅膜并设置有凹部。在凹部中，铜的反射器层被设置为阻挡层，其间具有阻挡金属。铜的反射层被氧化硅膜覆盖，并且在其上提供设有多个保险丝的保险丝区域。铜的反射层具有向下凹入的反射平面以反射激光束。铜的反射器层布置成基本上与整个熔断器区域重叠，如在平面中所见。照射熔断器的激光束可以对保险丝区域的附近产生减小的影响。可以获得尺寸减小的半导体装置。

2. 发明申请

US20070164394A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20070164394A1
公开(公告)日：2007-07-19
申请号：US11511442
申请日：2006-08-29
申请人： Yasuhiro Ido , Kazushi Kono , Takeshi Iwamoto
发明人： Yasuhiro Ido , Kazushi Kono , Takeshi Iwamoto
IPC分类号： H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： On a semiconductor substrate a silicon oxide film is formed and provided with a recess. In the recess a reflector layer of copper is disposed as a blocking layer with a barrier metal posed therebetween. The reflector layer of copper is covered with a silicon oxide film and thereon a fuse region provided with a plurality of fuses is provided. The reflector layer of copper has a plane of reflection recessed downward to reflect a laser beam. The reflector layer of copper is arranged to overlap substantially the entirety of the fuse region, as seen in a plane. A laser beam radiated to blow the fuse can have a reduced effect on a vicinity of the fuse region. A semiconductor device reduced in size can be obtained.
摘要翻译：在半导体衬底上形成氧化硅膜并设置有凹部。在凹部中，铜的反射器层被设置为阻挡层，其间具有阻挡金属。铜的反射层被氧化硅膜覆盖，并且在其上提供设有多个保险丝的保险丝区域。铜的反射层具有向下凹入的反射平面以反射激光束。铜的反射器层布置成基本上与整个熔断器区域重叠，如在平面中所见。照射熔断器的激光束可以对保险丝区域的附近产生减小的影响。可以获得尺寸减小的半导体装置。

3. 发明授权

US07034406B2 Semiconductor device with alignment mark 失效
标题翻译：具有对准标记的半导体器件
公开(公告)号：US07034406B2
公开(公告)日：2006-04-25
申请号：US10870976
申请日：2004-06-21
申请人： Yasuhiro Ido , Takeshi Iwamoto , Kazushi Kono
发明人： Yasuhiro Ido , Takeshi Iwamoto , Kazushi Kono
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device includes an alignment mark arranged on a surface, and including a high reflectance portion and a flat low reflectance portion; and a first silicon oxide film formed internally and provided with a plurality of first embedded portions filled with a material different from a material of portions around the embedded portions. The first embedded portions are formed in at least a portion of a region avoiding a portion shaded by projecting the high reflectance portion onto the silicon oxide film.
摘要翻译：半导体器件包括布置在表面上的对准标记，并且包括高反射率部分和平坦的低反射率部分; 以及第一氧化硅膜，其内部形成有多个第一嵌入部分，该第一嵌入部分填充有与嵌入部分周围的部分材料不同的材料。第一嵌入部分形成在区域的至少一部分中，避免通过将高反射率部分投影到氧化硅膜上而被遮蔽的部分。

4. 发明授权

US08723291B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US08723291B2
公开(公告)日：2014-05-13
申请号：US13592949
申请日：2012-08-23
申请人： Toshiaki Yonezu , Takeshi Iwamoto , Shigeki Obayashi , Masashi Arakawa , Kazushi Kono
发明人： Toshiaki Yonezu , Takeshi Iwamoto , Shigeki Obayashi , Masashi Arakawa , Kazushi Kono
IPC分类号： H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first the via hole wiring is surrounded.
摘要翻译：一种半导体集成电路，其可以使用电熔丝执行可靠的浮雕处理。半导体集成电路包括熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。保险丝布线被超过预定值的电流切断。第一电极焊盘连接到熔丝布线的一侧，第二电极焊盘连接到熔丝布线的另一侧，污染控制层通过绝缘体形成在熔丝布线的上层和下层中层。在熔丝配线中，在第一通孔配线的外侧形成有一对的第二通孔配线，以使第一通孔配线被包围。

5. 发明授权

US08487402B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08487402B2
公开(公告)日：2013-07-16
申请号：US12869323
申请日：2010-08-26
申请人： Kazushi Kono , Takeshi Iwamoto , Hisayuki Kato , Shigeki Obayashi , Toshiaki Yonezu
发明人： Kazushi Kono , Takeshi Iwamoto , Hisayuki Kato , Shigeki Obayashi , Toshiaki Yonezu
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered.A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.
摘要翻译：提供具有小占用面积的电直线状熔断器的半导体器件。多个突出部10f形成在从电熔丝部10a的中间位置偏离的位置，更具体地，形成在远离通孔10e和靠近通孔10d的位置。多个突出部20f形成在从电熔丝部20a的中间位置偏移的位置，更具体地，形成在远离通孔20d和靠近20e的位置。也就是说，突出部分10f和突出部分20f被布置成Z字形。

6. 发明授权

US08331185B2 Semiconductor device having electrical fuses with less power consumption and interconnection arrangement 有权
标题翻译：具有电功率消耗较小的电熔丝和互连配置的半导体器件
公开(公告)号：US08331185B2
公开(公告)日：2012-12-11
申请号：US12723218
申请日：2010-03-12
申请人： Shigeki Obayashi , Toshiaki Yonezu , Takeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Takahiro Uchida
发明人： Shigeki Obayashi , Toshiaki Yonezu , Takeshi Iwamoto , Kazushi Kono , Masashi Arakawa , Takahiro Uchida
IPC分类号： G11C17/18
CPC分类号： G11C17/18 , G11C17/165 , G11C29/027 , G11C29/028 , G11C29/785 , H01L23/5256 , H01L27/101 , H01L2924/0002 , H01L2924/00
摘要： In fuse program circuits, fuse element FS is implemented using metal interconnect at third or higher layer of multilayer metal interconnect. In each fuse program circuit, program information and fuse select information are sequentially transferred using a scan flip-flops, and fuses are selectively and electrically blown one by one. The fuse program circuit provided with fuse elements that can be programmed even after packaging is implemented with low power consumption and a low occupation area.
摘要翻译：在熔丝编程电路中，使用第三层或更高层多层金属互连的金属互连实施熔丝元件FS。在每个熔丝编程电路中，使用扫描触发器顺序传送程序信息和熔丝选择信息，并且一个接一个地选择性地电熔熔断器。设置有即使在封装之后也可以被编程的熔丝元件的保险丝编程电路以低功耗和低占用面积实现。

7. 发明申请

US20110006392A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110006392A1
公开(公告)日：2011-01-13
申请号：US12878977
申请日：2010-09-09
申请人： Kazushi Kono , Takeshi Iwamoto , Hisayuki Kato , Shigeki Obayashi , Toshiaki Yonezu
发明人： Kazushi Kono , Takeshi Iwamoto , Hisayuki Kato , Shigeki Obayashi , Toshiaki Yonezu
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered.A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.
摘要翻译：提供具有小占用面积的电直线状熔断器的半导体器件。多个突出部10f形成在从电熔丝部10a的中间位置偏离的位置，更具体地，形成在远离通孔10e和靠近通孔10d的位置。多个突出部20f形成在从电熔丝部20a的中间位置偏移的位置，更具体地，形成在远离通孔20d和靠近20e的位置。也就是说，突出部分10f和突出部分20f被布置成Z字形。

8. 发明申请

US20100320562A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100320562A1
公开(公告)日：2010-12-23
申请号：US12869323
申请日：2010-08-26
申请人： KAZUSHI KONO , Takeshi Iwamoto , Hisayuki Kato , Shigeki Obayashi , Toshiaki Yonezu
发明人： KAZUSHI KONO , Takeshi Iwamoto , Hisayuki Kato , Shigeki Obayashi , Toshiaki Yonezu
IPC分类号： H01L29/86
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered.A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.
摘要翻译：提供具有小占用面积的电直线状熔断器的半导体器件。多个突出部10f形成在从电熔丝部10a的中间位置偏离的位置，更具体地，形成在远离通孔10e和靠近通孔10d的位置。多个突出部20f形成在从电熔丝部20a的中间位置偏移的位置，更具体地，形成在远离通孔20d和靠近20e的位置。也就是说，突出部分10f和突出部分20f被布置成Z字形。

9. 发明授权

US08487403B2 Semiconductor device 有权
公开(公告)号：US08487403B2
公开(公告)日：2013-07-16
申请号：US12878977
申请日：2010-09-09
申请人： Kazushi Kono , Takeshi Iwamoto , Hisayuki Kato , Shigeki Obayashi , Toshiaki Yonezu
发明人： Kazushi Kono , Takeshi Iwamoto , Hisayuki Kato , Shigeki Obayashi , Toshiaki Yonezu
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： The semiconductor device which has an electric straight line-like fuse with a small occupying area is offered.A plurality of projecting portions 10f are formed in the position shifted from the middle position of electric fuse part 10a, and, more concretely, are formed in the position distant from via 10e and near via 10d. A plurality of projecting portions 20f are formed in the position shifted from the middle position of electric fuse part 20a, and, more concretely, are formed in the position distant from via 20d and near 20e. That is, projecting portions 10f and projecting portions 20f are arranged in the shape of zigzag.

10. 发明申请

US20130049166A1 SEMICONDUCTOR INTEGRATED CIRCUIT 有权
标题翻译：半导体集成电路
公开(公告)号：US20130049166A1
公开(公告)日：2013-02-28
申请号：US13592949
申请日：2012-08-23
申请人： Toshiaki YONEZU , Takeshi Iwamoto , Shigeki Obayashi , Masashi Arakawa , Kazushi Kono
发明人： Toshiaki YONEZU , Takeshi Iwamoto , Shigeki Obayashi , Masashi Arakawa , Kazushi Kono
IPC分类号： H01L23/62
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit which can perform reliable relief processing using an electric fuse. The semiconductor integrated circuit includes a fuse wiring, a first electrode pad, a second electrode pad, a pollution-control layer, and a first via hole wiring and a second via hole wiring. The fuse wiring is cut by a current exceeding a predetermined value. A first electrode pad is connected to one side of a fuse wiring, a second electrode pad is connected to the other of a fuse wiring, a pollution-control layer is formed in the upper layer and the lower layer of the fuse wiring via an insulating layer. In the fuse wiring, a second via hole wiring of a pair is formed in the outside of a first via hole wiring so that the first via hole wiring is surrounded.
摘要翻译：一种半导体集成电路，其可以使用电熔丝执行可靠的浮雕处理。半导体集成电路包括熔丝布线，第一电极焊盘，第二电极焊盘，污染控制层以及第一通孔布线和第二通孔布线。保险丝布线被超过预定值的电流切断。第一电极焊盘连接到熔丝布线的一侧，第二电极焊盘连接到熔丝布线的另一侧，污染控制层通过绝缘体形成在熔丝布线的上层和下层中层。在保险丝布线中，在第一通孔布线的外侧形成有一对第二通孔布线，使得第一通孔布线被包围。

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