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1. 发明授权

US08988160B2 Data transmission system and semiconductor circuit 有权
标题翻译：数据传输系统和半导体电路
公开(公告)号：US08988160B2
公开(公告)日：2015-03-24
申请号：US13004609
申请日：2011-01-11
申请人： Yasuhiro Ikeda , Yutaka Uematsu , Satoshi Muraoka
发明人： Yasuhiro Ikeda , Yutaka Uematsu , Satoshi Muraoka
IPC分类号： H03H2/00 , H03H7/38 , H04B3/02
CPC分类号： H04B3/02
摘要： A data transmission system is provided in which it is possible to perform both of suppressing the degrading of the slew rate and suppressing the ringing even if load capacitance of an input buffer is changed.The data transmission system transmitting data from an output buffer to the input buffer through a trace is provided with first RC parallel circuits connected in series to the trace on a first Printed Circuit Board (PCB) on which the output buffer is mounted, and second RC parallel circuits connected in series to the trace on a second Printed Circuit Board (PCB) on which the input buffer is mounted, and which can be connected and separated to and from the first Printed Circuit Board (PCB).
摘要翻译：提供了一种数据传输系统，其中即使输入缓冲器的负载电容改变，也可以同时执行抑制转换速率的降级和抑制振铃的两者。通过轨迹将数据从输出缓冲器传输到输入缓冲器的数据传输系统提供有与其上安装有输出缓冲器的第一印刷电路板（PCB）上的迹线串联连接的第一RC并联电路，以及第二RC 并联电路与安装有输入缓冲器的第二印刷电路板（PCB）上的迹线串联连接，并且可以与第一个印刷电路板（PCB）连接和分离。

2. 发明授权

US08581622B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08581622B1
公开(公告)日：2013-11-12
申请号：US13512465
申请日：2012-05-16
申请人： Yasuhiro Ikeda , Yutaka Uematsu , Satoshi Muraoka
发明人： Yasuhiro Ikeda , Yutaka Uematsu , Satoshi Muraoka
IPC分类号： H03K17/16
CPC分类号： G11C7/10 , G11C7/1057 , G11C7/1084
摘要： To suppress power consumption and enhance signal quality as compared with the case where first and second semiconductor elements are terminated only by on-chip input termination resistor circuits. A first semiconductor element with a switching function and a second semiconductor element with a switching function are connected to each other with a substrate interconnection, and a resistor element is connected in parallel with the substrate interconnection. The resistor element is placed at an arbitrary position or a branch point on the signal interconnection.
摘要翻译：与第一和第二半导体元件仅由片上输入终端电阻电路端接的情况相比，抑制功耗和提高信号质量。具有开关功能的第一半导体元件和具有开关功能的第二半导体元件通过衬底互连彼此连接，并且电阻元件与衬底互连并联连接。电阻元件放置在信号互连的任意位置或分支点处。

3. 发明申请

US20130307582A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130307582A1
公开(公告)日：2013-11-21
申请号：US13512465
申请日：2012-05-16
申请人： Yasuhiro Ikeda , Yutaka Uematsu , Satoshi Muraoka
发明人： Yasuhiro Ikeda , Yutaka Uematsu , Satoshi Muraoka
IPC分类号： H03K17/16
CPC分类号： G11C7/10 , G11C7/1057 , G11C7/1084
摘要： To suppress power consumption and enhance signal quality as compared with the case where first and second semiconductor elements are terminated only by on-chip input termination resistor circuits. A first semiconductor element with a switching function and a second semiconductor element with a switching function are connected to each other with a substrate interconnection, and a resistor element is connected in parallel with the substrate interconnection. The resistor element is placed at an arbitrary position or a branch point on the signal interconnection.
摘要翻译：与第一和第二半导体元件仅由片上输入终端电阻电路端接的情况相比，抑制功耗和提高信号质量。具有开关功能的第一半导体元件和具有开关功能的第二半导体元件通过衬底互连彼此连接，并且电阻元件与衬底互连并联连接。电阻元件放置在信号互连的任意位置或分支点处。

4. 发明申请

US20120262885A1 SIGNAL TRANSFER CIRCUIT 审中-公开
标题翻译：信号传输电路
公开(公告)号：US20120262885A1
公开(公告)日：2012-10-18
申请号：US13358540
申请日：2012-01-26
申请人： Yasuhiro IKEDA , Yutaka Uematsu , Satoshi Muraoka
发明人： Yasuhiro IKEDA , Yutaka Uematsu , Satoshi Muraoka
IPC分类号： H05K1/18
CPC分类号： H05K1/0243 , H05K1/0251 , H05K1/115 , H05K2201/09227 , H05K2201/09772 , H05K2201/10545 , H05K2201/10689
摘要： Provided is a signal transfer circuit which uses a low cost circuit board with a high packing density but is capable of reducing a crosstalk noise between signal lines and also reducing a reflection noise due to a stub. A signal transfer circuit of the present invention is configured such that lead terminals of electronic components and through-hole vias are connected to each other by surface wirings, respectively, to allow no branching from the middle of the through-hole vias. Further, first wirings connecting a first electronic component are each arranged between a corresponding pair of second wirings connecting a second electronic component, and signals are transmitted through the first wirings and the second wirings by interleaved transmission.
摘要翻译：提供了一种使用具有高包装密度的低成本电路板的信号传输电路，但是能够减少信号线之间的串扰噪声并且还减少由于短截线引起的反射噪声。本发明的信号传输电路被配置为使得电子部件和通孔过孔的引线端子分别通过表面布线彼此连接，以便不允许从通孔过孔的中间分支。此外，连接第一电子部件的第一布线分别布置在连接第二电子部件的相应的一对第二布线之间，并且信号通过交错传输通过第一布线和第二布线传输。

5. 发明授权

US08866282B2 Semiconductor apparatus, signal transmission system and signal transmission method 有权
标题翻译：半导体装置，信号传输系统和信号传输方法
公开(公告)号：US08866282B2
公开(公告)日：2014-10-21
申请号：US13586104
申请日：2012-08-15
申请人： Yasuhiro Ikeda , Yutaka Uematsu , Satoshi Muraoka
发明人： Yasuhiro Ikeda , Yutaka Uematsu , Satoshi Muraoka
IPC分类号： H01L23/52 , H04L25/02 , H05K1/02 , H01L49/02 , H01L23/12
CPC分类号： H01L28/20 , H01L23/12 , H01L23/5228 , H01L2224/16225 , H04L25/02 , H04L25/0272 , H04L25/0288 , H05K1/02 , H05K1/0234 , H05K1/0246 , H05K1/025 , H05K2201/10022 , H05K2201/10159
摘要： A slew rate of a signal transmitted between a semiconductor device having a small load capacitance and a semiconductor device having a large load capacitance is improved. When a signal is transmitted to the semiconductor device (for example, a memory device) having the large load capacitance, pre-emphasis is performed, and when a signal is transmitted to the semiconductor device (for example, a memory controller) having the small load capacitance, pre-emphasis is not performed or is slightly performed. By this, when the signal is transmitted to the memory device, blunting in signal rising due to the load capacitance is suppressed, and when the signal is transmitted to the memory controller, ringing due to the reflection of the signal is suppressed, and the slew rate of the data transmission is improved.
摘要翻译：在具有小负载电容的半导体器件和具有大负载电容的半导体器件之间传输的信号的转换速率得到改善。当信号被发送到具有大的负载电容的半导体器件（例如，存储器件）时，执行预加重，并且当信号被发送到具有小的负载电容的半导体器件（例如，存储器控制器）负载电容，预加重不执行或略微执行。由此，当信号被发送到存储装置时，由于负载电容而导致的信号上升的钝化被抑制，并且当信号被发送到存储器控制器时，由于信号的反射而被抑制的振铃数据传输速率提高。

6. 发明申请

US20130207234A1 SEMICONDUCTOR APPARATUS, SIGNAL TRANSMISSION SYSTEM AND SIGNAL TRANSMISSION METHOD 有权
标题翻译：半导体装置，信号传输系统和信号传输方法
公开(公告)号：US20130207234A1
公开(公告)日：2013-08-15
申请号：US13586104
申请日：2012-08-15
申请人： Yasuhiro Ikeda , Yutaka Uematsu , Satoshi Muraoka
发明人： Yasuhiro Ikeda , Yutaka Uematsu , Satoshi Muraoka
IPC分类号： H01L49/02
CPC分类号： H01L28/20 , H01L23/12 , H01L23/5228 , H01L2224/16225 , H04L25/02 , H04L25/0272 , H04L25/0288 , H05K1/02 , H05K1/0234 , H05K1/0246 , H05K1/025 , H05K2201/10022 , H05K2201/10159
摘要： A slew rate of a signal transmitted between a semiconductor device having a small load capacitance and a semiconductor device having a large load capacitance is improved. When a signal is transmitted to the semiconductor device (for example, a memory device) having the large load capacitance, pre-emphasis is performed, and when a signal is transmitted to the semiconductor device (for example, a memory controller) having the small load capacitance, pre-emphasis is not performed or is slightly performed. By this, when the signal is transmitted to the memory device, blunting in signal rising due to the load capacitance is suppressed, and when the signal is transmitted to the memory controller, ringing due to the reflection of the signal is suppressed, and the slew rate of the data transmission is improved.
摘要翻译：在具有小负载电容的半导体器件和具有大负载电容的半导体器件之间传输的信号的转换速率得到改善。当信号被发送到具有大的负载电容的半导体器件（例如，存储器件）时，执行预加重，并且当信号被发送到具有小的负载电容的半导体器件（例如，存储器控制器）负载电容，预加重不执行或略微执行。由此，当信号被发送到存储装置时，由于负载电容而导致的信号上升的钝化被抑制，并且当信号被发送到存储器控制器时，由于信号的反射而被抑制的振铃数据传输速率提高。

7. 发明授权

US08680881B2 Test method and interposer used therefor 失效
标题翻译：用于此的测试方法和插入器
公开(公告)号：US08680881B2
公开(公告)日：2014-03-25
申请号：US13044717
申请日：2011-03-10
申请人： Yutaka Uematsu , Hideki Osaka , Satoshi Nakamura , Satoshi Muraoka , Mitsuaki Katagiri , Ken Iwakura , Yukitoshi Hirose
发明人： Yutaka Uematsu , Hideki Osaka , Satoshi Nakamura , Satoshi Muraoka , Mitsuaki Katagiri , Ken Iwakura , Yukitoshi Hirose
IPC分类号： G01R31/00
CPC分类号： G01R31/2889
摘要： An interposer to be mounted with an integrated circuit to be a test object is provided with a switch and a probe to detect an electric current corresponding to individual terminals of the integrated circuit. A test pattern signal is then inputted to the integrated circuit through a test substrate as a switch that is connected to a power supply terminal of the integrated circuit and that is turned off. If the integrated circuit normally operates and the current values of all the terminals of the integrated circuit are within a tolerance, the power supply terminal connected to the turned-off switch is identified as a terminal that may be removed.
摘要翻译：安装有作为测试对象的集成电路的插入器设置有用于检测与集成电路的各个端子相对应的电流的开关和探头。然后，通过作为与集成电路的电源端子连接并断开的开关的测试基板将测试图形信号输入到集成电路。如果集成电路正常工作，并且集成电路的所有端子的电流值都在容差内，则连接到关断开关的电源端子被识别为可以被去除的端子。

8. 发明授权

US5844762A Electronic circuit device having a function of inhibiting resonance in power wiring 失效
标题翻译：具有抑制电力布线中的谐振功能的电子电路装置
公开(公告)号：US5844762A
公开(公告)日：1998-12-01
申请号：US762691
申请日：1996-12-12
申请人： Hideho Yamamura , Masakazu Yamamoto , Naoki Maru , Satoshi Muraoka
发明人： Hideho Yamamura , Masakazu Yamamoto , Naoki Maru , Satoshi Muraoka
IPC分类号： H03H7/01 , G06F1/26 , H03H2/00 , H05K1/02 , H05K3/46 , H05K9/00 , H02H3/22
CPC分类号： H05K1/0234 , H05K1/0231 , H05K2201/09309 , H05K2201/10022 , H05K2201/10522 , H05K2201/10689
摘要： An electronic circuit device having a power wiring resonance inhibition function includes a plurality of electronic circuit elements, and a wiring board having the electronic circuit elements disposed thereon. The wiring board includes a plurality of planar power supply wires for supplying power to the electronic circuit elements. The planar power wires include a pair of planar power supply wires for supplying power to the electronic circuit elements at a predetermined voltage. The electronic circuit device also includes a plurality of damping elements disposed at a plurality of positions on the wiring board. The damping elements are connected between the pair of planar power supply wires at a plurality of positions on the pair of planar power supply wires. The damping elements reduce power supply system impedance and inhibit power wiring system resonance, thereby reducing supply voltage fluctuation caused by the power wiring system resonance and noise caused by the supply voltage fluctuation.
摘要翻译：具有电力线共振抑制功能的电子电路装置包括多个电子电路元件，以及配置有电子电路元件的布线基板。布线板包括用于向电子电路元件供电的多个平面电源线。平面电力线包括用于以预定电压向电子电路元件供电的一对平面电源线。电子电路装置还包括布置在布线板上的多个位置处的多个阻尼元件。阻尼元件在一对平面电源线的多个位置处连接在一对平面电源线之间。阻尼元件降低了电源系统的阻抗，并阻止了电源线路系统的共振，从而减少了由电源线路系统引起的电源电压波动和由电源电压波动引起的噪声。

9. 发明授权

US07969197B2 Output buffer circuit and differential output buffer circuit, and transmission method 有权
标题翻译：输出缓冲电路和差分输出缓冲电路及其传输方式
公开(公告)号：US07969197B2
公开(公告)日：2011-06-28
申请号：US12716796
申请日：2010-03-03
申请人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
发明人： Satoshi Muraoka , Norio Chujo , Ritsuro Orihashi
IPC分类号： H03K19/094
CPC分类号： H03K19/018521
摘要： An output buffer includes inverters, a delay circuit for delaying an input signal, buffers and switches. The output buffer transmits a logic signal to a transmission path and, in accordance with an amount of signal attenuation in the transmission path, creates a waveform including four or more kinds of signal voltages. The buffers are redundantly connected in parallel, and the number of buffers concurrently turn ON is controlled by respective switches provided in series with output resistors of the buffers. By selecting the buffers of switches which are turned ON, the preemphasis amount and a number of preemphasis taps are adjusted through a selector logic selection signal so that the preemphasis amount is made variable and the ON resistance of the buffers is made constant.
摘要翻译：输出缓冲器包括反相器，用于延迟输入信号的延迟电路，缓冲器和开关。输出缓冲器将逻辑信号发送到传输路径，并且根据传输路径中的信号衰减量产生包括四种或更多种信号电压的波形。缓冲器并联冗余连接，同时导通的缓冲器的数量由与缓冲器的输出电阻器串联提供的相应开关控制。通过选择接通的开关的缓冲器，通过选择器逻辑选择信号调整预加重量和预加重抽头数，使预加重量变为可变，并使缓冲器的导通电阻保持恒定。

10. 发明授权

US06993633B1 Computer system utilizing speculative read requests to cache memory 失效
标题翻译：计算机系统利用推测读请求来缓存内存
公开(公告)号：US06993633B1
公开(公告)日：2006-01-31
申请号：US09628718
申请日：2000-07-28
申请人： Tadayuki Sakakibara , Isao Ohara , Hideya Akashi , Yuji Tsushima , Satoshi Muraoka
发明人： Tadayuki Sakakibara , Isao Ohara , Hideya Akashi , Yuji Tsushima , Satoshi Muraoka
IPC分类号： G06F9/38
CPC分类号： G06F12/0862 , G06F12/084
摘要： A cache data control system and method for a computer system in which in a memory read processing, a coherent controller issues an advanced speculative read request for (speculatively) reading data from a cache data section in advance to a cache data controller, before reading a cache tag from a cache tag section and conducting cache hit check. If a cache hit has occurred, the cache data controller returns the data subjected to speculative reading as response data, at the time when the cache data controller has received a read request issued by the coherent controller.
摘要翻译：一种用于计算机系统的高速缓存数据控制系统和方法，其中在存储器读取处理中，相干控制器在读取之前向高速缓存数据控制器发送用于（推测性地）将数据从高速缓存数据部分读取的高级推测性读请求缓存标签从缓存标签部分进行缓存命中检查。如果发生了高速缓存命中，则高速缓存数据控制器接收到由相干控制器发出的读请求时，将经过推测读取的数据作为响应数据返回。

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