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1. 发明授权

US06549198B1 Hout position control circuit 失效
标题翻译： Hout位置控制电路
公开(公告)号：US06549198B1
公开(公告)日：2003-04-15
申请号：US09456816
申请日：1999-12-08
申请人： Yoshiyuki Uto , Takafumi Esaki , Hiroshi Furukawa , Yasuhiro Fukuda
发明人： Yoshiyuki Uto , Takafumi Esaki , Hiroshi Furukawa , Yasuhiro Fukuda
IPC分类号： G09G500
CPC分类号： G09G1/167 , G09G2340/0478 , H04N5/126 , H04N5/46
摘要： Disclosed is a HOUT position control circuit used to control the horizontal position of display image in a multisync monitor. The circuit has: a first PLL circuit that is phase-locked with input horizontal synchronous signal; a second PLL circuit that is phase-locked with output of the first PLL circuit; and a circuit for generating a delay between outputs of the first PLL circuit and the second PLL circuit to control the delay amount from the input horizontal synchronous signal to output horizontal drive signal.
摘要翻译：公开了用于控制多同步监视器中的显示图像的水平位置的HOUT位置控制电路。该电路具有：与输入水平同步信号锁相的第一个PLL电路; 与所述第一PLL电路的输出锁相的第二PLL电路; 以及用于在第一PLL电路和第二PLL电路的输出之间产生延迟以控制从输入水平同步信号到输出水平驱动信号的延迟量的电路。

2. 发明授权

US06222400B1 Lock-in detecting circuit having variable window for checking phase locked loop and method used therein 失效
标题翻译：具有用于检查锁相环的可变窗口的锁定检测电路及其中使用的方法
公开(公告)号：US06222400B1
公开(公告)日：2001-04-24
申请号：US09472950
申请日：1999-12-27
申请人： Yasuhiro Fukuda , Takafumi Esaki , Yoshiyuki Uto , Hiroshi Furukawa
发明人： Yasuhiro Fukuda , Takafumi Esaki , Yoshiyuki Uto , Hiroshi Furukawa
IPC分类号： H03L700
CPC分类号： H03L7/095 , H04N5/126 , H04N5/46
摘要： A phase locked loop makes a system clock signal synchronous to a horizontal synchronizing signal for a display unit, and a lock-in detecting circuit monitors said phase locked loop to see whether or not a phase difference takes place between the system clock signal and the horizontal synchronizing signal, wherein the lock-in detecting circuit measures the unlocked state between the system clock signal and the horizontal synchronizing signal in a window defined in a vertical synchronizing period and, thereafter, compares the time period of the unlocked state with a critical value to see whether or not the unlocked state is due to a temporary phenomenon or a phase difference to be corrected so that an detecting signal of the lock-in detecting circuit is reliable.
摘要翻译：锁相环使系统时钟信号与用于显示单元的水平同步信号同步，并且锁定检测电路监视所述锁相环，以查看在系统时钟信号和水平面之间是否发生相位差同步信号，其中所述锁定检测电路在垂直同步周期中定义的窗口中测量所述系统时钟信号和所述水平同步信号之间的解锁状态，然后将所述解锁状态的时间周期与临界值进行比较查看解锁状态是否由于临时现象或相位差被校正，使得锁定检测电路的检测信号是可靠的。

3. 发明授权

US06486857B1 Deflection correction circuit for narrowing a pull-in range of a VCO to reduce frequency variations in a horizontal synchronizing signal 失效
标题翻译：用于缩小VCO的拉入范围以减小水平同步信号中的频率变化的偏转校正电路
公开(公告)号：US06486857B1
公开(公告)日：2002-11-26
申请号：US09503177
申请日：2000-02-14
申请人： Takafumi Esaki , Yoshiyuki Uto , Hiroshi Furukawa , Yasuhiro Fukuda
发明人： Takafumi Esaki , Yoshiyuki Uto , Hiroshi Furukawa , Yasuhiro Fukuda
IPC分类号： G09G108
CPC分类号： H03L7/197 , G09G1/04 , G09G5/18 , H03L7/18
摘要： There is disclosed a phase-locked loop (PLL) circuit for use in an improved deflection correction circuit for a larger and flat display device. The PLL circuit has a phase comparator circuit, a filter, and a voltage-controlled oscillator (VCO) connected in series in this order. The output signal from the VCO is fed back to the phase comparator circuit. The PLL circuit further includes a period-detecting circuit for detecting the period of an externally applied signal and a frequency divider circuit. This frequency divider circuit divides the frequency of the output signal from the VCO according to the period detected by the period-detecting circuit and feeds the resulting signal back to the VCO.
摘要翻译：公开了一种用于更大和平坦的显示装置的改进的偏转校正电路中的锁相环（PLL）电路。 PLL电路具有按顺序串联连接的相位比较器电路，滤波器和压控振荡器（VCO）。来自VCO的输出信号被反馈到相位比较器电路。 PLL电路还包括用于检测外部施加的信号的周期的周期检测电路和分频器电路。该分频器电路根据由周期检测电路检测到的周期来分频来自VCO的输出信号的频率，并将所得到的信号反馈给VCO。

4. 发明授权

US06275553B1 Digital PLL circuit and clock generation method 失效
标题翻译：数字PLL电路和时钟生成方法
公开(公告)号：US06275553B1
公开(公告)日：2001-08-14
申请号：US09247354
申请日：1999-02-10
申请人： Takafumi Esaki
发明人： Takafumi Esaki
IPC分类号： H04L2536
CPC分类号： H03L7/23 , H03L7/0996
摘要： A digital PLL circuit is formed by a first digital PLL circuit, a signal generation circuit that generates a plurality of signals that have the same frequency as the output of the first PLL circuit but differing phases, and the second digital PLL circuit having a signal selecting circuit that can select the signals from the signal generation circuit, a frequency divider circuit that divides the output signal of the signal selecting circuit, a phase comparator circuit that compares the phase between the a signal used as a reference and the output signal from the frequency divider circuit, an up/down counter that detects the phase difference of the phase comparison circuit, and a digital filter that is provided between the up/down counter and the signal selecting circuit, the second PLL circuit selecting the signals from the signal generation circuit based on the output from the up/down counter.
摘要翻译：数字PLL电路由第一数字PLL电路，信号产生电路形成，该信号产生电路产生与第一PLL电路的输出具有相同频率但具有相位相同频率的多个信号，第二数字PLL电路具有信号选择电路，其可以选择来自信号发生电路的信号，分频电路，其分频信号选择电路的输出信号;相位比较器电路，其比较用作参考的信号和来自频率的输出信号之间的相位分频器电路，检测相位比较电路的相位差的上/下计数器和设置在上/下计数器和信号选择电路之间的数字滤波器，第二PLL电路从信号发生电路中选择信号基于上/下计数器的输出。

5. 发明授权

US6133900A OSD device capable of maintaining the size of displayed OSD data at a constant in a multisync monitor regardless of a frequency of a horizontal synchronous signal 失效
标题翻译： OSD设备能够在多同步监视器中将显示的OSD数据的大小保持在恒定，而不管水平同步信号的频率如何
公开(公告)号：US6133900A
公开(公告)日：2000-10-17
申请号：US971962
申请日：1997-11-17
申请人： Takafumi Esaki
发明人： Takafumi Esaki
IPC分类号： G09G1/16 , G09G5/00 , G09G5/22 , H03L7/08 , H04N5/12 , H04N5/445 , H04N5/46 , H04N5/44
CPC分类号： H04N5/44504 , H04N5/46 , H04N5/126
摘要： An OSD clock generating circuit includes a PPL circuit controlled to oscillate to generate an OSD clock signal phase-locked with a level transition point of a horizontal synchronous signal. When an OSD device is used in a multisync monitor capable of changing its horizontal synchronous signal frequency, an OSD data can be displayed with the same size without being influenced by a change of the frequency of the horizontal synchronous signal.
摘要翻译： OSD时钟发生电路包括被控制振荡以产生与水平同步信号的电平转变点锁相的OSD时钟信号的PPL电路。当在能够改变其水平同步信号频率的多同步监视器中使用OSD设备时，可以以相同大小显示OSD数据，而不受水平同步信号的频率变化的影响。

6. 发明授权

US06456217B1 Digital/analog converter having delta-sigma type pulse modulation circuit 失效
标题翻译：具有Δ-Σ型脉冲调制电路的数/模转换器
公开(公告)号：US06456217B1
公开(公告)日：2002-09-24
申请号：US09653749
申请日：2000-09-01
申请人： Takafumi Esaki
发明人： Takafumi Esaki
IPC分类号： H03M106
CPC分类号： H03M1/66 , H03M7/3028 , H03M7/3031
摘要： In a digital/analog converter for (m+n)-bit, digital input data, a sigma-delta type pulse modulation circuit receives lower-order n bits of the digital input data to generate 1-bit data corresponding to the lower-order n bits in synchronization with a clock signal. An m-bit adder adds the 1-bit data to upper-order m bits of the digital input data. An m-bit digital/analog conversion section performs a digital-to-analog conversion upon an output value of the m-bit adder. A low-pass filter removes a high frequency component of an output value of the m-bit digital/analog conversion section to generate an analog data corresponding to the (m+n)-bit digital input data.
摘要翻译：在用于（m + n）位数字输入数据的数/模转换器中，Σ-Δ型脉冲调制电路接收数字输入数据的低阶n位以产生对应于低阶的1位数据 n位与时钟信号同步。 m位加法器将1位数据加到数字输入数据的高位m位。 m位数字/模拟转换部分根据m位加法器的输出值执行数模转换。低通滤波器去除m位数字/模拟转换部分的输出值的高频分量，以产生对应于（m + n）位数字输入数据的模拟数据。

7. 发明授权

US5181099A Composite video signal generator 失效
标题翻译：复合视频信号发生器
公开(公告)号：US5181099A
公开(公告)日：1993-01-19
申请号：US800566
申请日：1991-11-27
申请人： Takafumi Esaki
发明人： Takafumi Esaki
IPC分类号： H04N9/00 , H04N9/64
CPC分类号： H04N9/641
摘要： Disclosed is a composite video generator comprising a color signal generating means, a color selecting means and an output means, and further being provided with a color change detecting means and a low amplitude color signal generating means. The composite video signal generator which combines a composite video input signal with a color signal as a character signal in accordance with a character data presence/absence signal to output the resultant signal as a composite video output signal. The composite video signal generator detects changes in the color signal and character data presence/absence signal and lowers the amplitude of the color signal at each change point, thereby suppressing the occurrence of a dot disturbance and color mixture.
摘要翻译：公开了一种复合视频发生器，其包括彩色信号发生装置，颜色选择装置和输出装置，并且还具有颜色变化检测装置和低幅度彩色信号产生装置。复合视频信号发生器，其根据字符数据存在/不存在信号将复合视频输入信号和彩色信号组合为字符信号，以将合成信号输出为复合视频输出信号。复合视频信号发生器检测颜色信号和字符数据存在/不存在信号的变化，并降低每个变化点处的颜色信号的幅度，从而抑制点干扰和混色的发生。

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