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1. 发明专利

JPS5670412A MEASURING METHOD FOR FLOW RATE BY SEPARATOR AND METERING TANK 失效
公开(公告)号：JPS5670412A
公开(公告)日：1981-06-12
申请号：JP14821979
申请日：1979-11-14
申请人： YANO TOSHIO , TANAKA MAMORU
发明人： YANO TOSHIO , TANAKA MAMORU
IPC分类号： G01F1/00 , G01F1/30
摘要： PURPOSE:To shorten the time required for injection and enable measurement of large flow rate by a method wherein the flow-channel-shaped separator having, at the upper end thereof, a pair of sharp and parallel edges having a fixed from of cross section is passed linearly across the flow of the downstream part of a fluid at a fixed speed, while the fluid passing through the separator is injected into the metering tank and the flow rate is measured from the quantity of injection and the time for injection. CONSTITUTION:The separator 4 composed of a pair of separating plates 41 and 42 having, at the upper end thereof, a pair of sharp and parallel edges 411 and 421 having a fixed form of cross section and of side plates 43 and 44 is moved at a fixed speed across the fluid from one side to the other side e of the downstream part 7 shown by broken lines by a moving device 5 consisting of a driving part 51 and a connecting rod 52. Only the fluid passing through the separator 4 is injected into the metering tank 6. The time of for injection can be detected by a mechanical, electrical or optical method. Accordingly, the flow rate is found by dividing the quantity of injection by the time for injection. By this, the time for injection is shortened and thus the measurement of large flow rate can be performed.

2. 发明申请

WO0170931A8 A MAMMALIAN OOCYTE-SPECIFIC LINKER HISTONE GENE H1oo 审中-公开
标题翻译：哺乳动物特异性接头Histone基因H1oo
公开(公告)号：WO0170931A8
公开(公告)日：2002-02-28
申请号：PCT/US0109366
申请日：2001-03-22
申请人： UNIV UTAH RES FOUND , ADASHI ELI , HENNEBOLD JON , TANAKA MAMORU
发明人： ADASHI ELI , HENNEBOLD JON , TANAKA MAMORU
IPC分类号： C07K14/47 , C07H17/00 , C07K14/00
CPC分类号： C07K14/47

3. 发明申请

WO0170931A9 A MAMMALIAN OOCYTE-SPECIFIC LINKER HISTONE GENE H1oo 审中-公开
标题翻译： MAMMALIAN OOCYTE-SPECIFIC LINKER HISTONE GENE H1oo
公开(公告)号：WO0170931A9
公开(公告)日：2002-12-19
申请号：PCT/US0109366
申请日：2001-03-22
申请人： UNIV UTAH RES FOUND , ADASHI ELI , HENNEBOLD JON , TANAKA MAMORU
发明人： ADASHI ELI , HENNEBOLD JON , TANAKA MAMORU
IPC分类号： C07K14/47 , C07H17/00 , C07K14/00
CPC分类号： C07K14/47

4. 发明专利

JPH0816688A PERIODIC CHAOS GENERATION CIRCUIT BY FREQUENCY CONTROL 失效
公开(公告)号：JPH0816688A
公开(公告)日：1996-01-19
申请号：JP14508294
申请日：1994-06-27
申请人： TANAKA MAMORU
发明人： FUAMU KONKA , TANAKA MAMORU , SHONO KATSUFUSA
IPC分类号： G06G7/26 , H03B29/00
摘要： PURPOSE:To simplify a chaos generation circuit and to realize a small-scaled circuit element by generating a periodic or chaotic waveform by an inverter circuit and a sampling and hold circuit. CONSTITUTION:A sampling hold circuit is composed in a form that a hold capacitor is inserted between the connection point of an inverter circuit composed of a resistor and an MOS transistor connected serially to each other and two serially connected CMOS switch circuits and ground. A periodic or chaotic waveform is generated as the input/output characteristic of the inverter circuit by repeating the operation of turning off a CMOS switch when a CMOS switch out of the two CMOS switches is turned on and applying the control of the sampling frequency of the sampling hold circuit. Therefore, a chaos generation circuit can be simplified and a small-scaled circuit element can be realized.

5. 发明专利

JPH02307152A INFORMATION COMPRESSING METHOD USING ASSOCIATIVE NEURAL NET 失效
公开(公告)号：JPH02307152A
公开(公告)日：1990-12-20
申请号：JP12956489
申请日：1989-05-23
申请人： TANAKA MAMORU
发明人： TANAKA MAMORU
IPC分类号： G06F15/18 , G06N3/00 , G06N99/00
摘要： PURPOSE:To attain the large scale integration by compressing the information with use of a digital neural net (DNN), i.e., SANNET for formation of a net and a robust state. CONSTITUTION:At learning the complete information is encoded as the informa tion series based on the code graph logic, and the redundant series of code words showing a closed circuit 19 of a graph or a cassette. Then the information is compressed via a DNN 17 in an associate state. That is, the nodal point syndrome is calculated at each nodal point 18 based on the information on the redundant series stored already in a 2nd branch assembly 20 when the incomplet or compete information series that has an error to the information series received at learning is given to a 1st branch assembly 21. In this case, the associate state is secured by correcting the information on a branch formed on the minimum path set between the nodal points which produce the nodal point syndrome s(ni) that is not equal to zero. As a result, the large scale inte gration is attained.

6. 发明专利

JPH02165369A ASSOCIATIVE MEMORY 失效
公开(公告)号：JPH02165369A
公开(公告)日：1990-06-26
申请号：JP32148088
申请日：1988-12-20
申请人： TANAKA MAMORU
发明人： TANAKA MAMORU , OSUGE YOSHIYUKI
IPC分类号： G06F15/18 , G06N3/04 , G06N99/00 , G11C15/00 , G11C15/04
摘要： PURPOSE:To improve the performance of an associative memory and the degree of integration by calculating a Hamming distance between respective information in plural fields in inputted retrieval data and their corresponding self-completion information in each field and associating data having high similarity to the retrieval data in the ascending order of a total Hamming distance obtained by summing the Hamming distances of plural fields. CONSTITUTION:An associative memory operation means 1 stores self-completion information or mutual completion information corresponding to the self-completion information at the time of learning, and at the time of association, executes logical operation between retrieval data and the stored information. An inter-code distance calculating means 2 calculates an inter-code distance between incomplete information having amibiguity corresponding to the inter-code distance of the self-completion information and the self-completion information at the time of association. A decision means 3 activates the storing addresses of the incomplete information and the complete information having a small inter-code distance and a data associating means 4 applies the activated address information to a memory to associate data correspond to the self-associated or mutually associated complete information from the memory. Consequently, the performance can be improved and integration can be made easy.

7. 发明专利

JPH0225290B2 失效
公开(公告)号：JPH0225290B2
公开(公告)日：1990-06-01
申请号：JP2466781
申请日：1981-02-21
申请人： MORI SHINSAKU , TANAKA MAMORU
发明人： MORI SHINSAKU , TANAKA MAMORU , YAMAMOTO MASAHIRO , NAKAMURA KAZUO
IPC分类号： H03H19/00

8. 发明专利

JPH01240018A ANALOG/DIGITAL CONVERTER 失效
公开(公告)号：JPH01240018A
公开(公告)日：1989-09-25
申请号：JP6585888
申请日：1988-03-22
申请人： TANAKA MAMORU
发明人： CHIGUSA YASUTAMI , TANAKA MAMORU
IPC分类号： H03M1/44
摘要： PURPOSE:To obtain a high speed and high accuracy AD converter by quantizing an analog input, outputting a most significant order bit train, feeding-back the output of the analog integrator of that time to a selecting means, executing quantization to make the output the analog input newly, outputting the next high-order bit train and repeating an operation subsequently in the same way. CONSTITUTION:A bit number to be converted is divided into several blocks in advance. At first, the basic operation of a sigma/delta/AD conversion is executed by necessary number of times to the most significant bit train. Next, the output of an analog integrator 1 at the final time is made to the analog input of a selecting means 2 newly, and the basic operation is executed by the necessary number of times. Subsequently, the conversion of the bit train is executed in order from high-order. When the basic operations of (n) number of times are divided into the two blocks, first, the basic operations of (m) number of times are executed, and next, the basic operations of (n-m) number of times are executed with the output of the analog integrator 1 at a previous stage as the new analog input. In the case of b=1, n=128 and m=64, for instance, the AD converter of 7 bits can be realized in an existing system, and the A/D converter of 12 bits can be realized in this system.

9. 发明专利

JPS61175774A COMPUTER FOR ANALYSIS OF SIMULTANEOUS EQUATIONS 失效
公开(公告)号：JPS61175774A
公开(公告)日：1986-08-07
申请号：JP1744585
申请日：1985-01-30
申请人： TANAKA MAMORU
发明人： TANAKA MAMORU , ASAI HIDEKI , ASAI MITSUO
IPC分类号： G06F17/16 , G06F15/78 , G06F17/12
摘要： PURPOSE:To attain the LU analysis of a spurse matrix with high efficiency by storing only the non-zero elements into a local memory of each local unit after ignoring the greater part of the zero elements of an original matrix Y to convert the matrix Y into a band matrix and flowing the elements successively in parallel and every line to (q) pieces of processors corresponding to the band width. CONSTITUTION:This processor contains (q) pieces of local units. Then, the local units 1-3 are all connected with each other via a common data bus 10, a control line 11, a priority circuit 12, etc. All non-zero elements only including the fill-in are stored in each local memory unit {Aj} in the row direction of a matrix after ignoring all zero elements. The operations of the processor are controlled in a division mode (a), a multiplication mode (b) and a gauss erasion mode (c) respectively. In the division mode the unit {Aj} receives an access by a counter 13. Only the local bus corresponding to a pivot aii is enabled by an enabling circuit 15. Then the pivot data aii are transferred to all local processors via a common bus.

10. 发明专利

JPS57131114A SWITCHED CAPACITOR FILTER 失效
公开(公告)号：JPS57131114A
公开(公告)日：1982-08-13
申请号：JP1571081
申请日：1981-02-06
申请人： TANAKA MAMORU , MORI SHINSAKU
发明人： TANAKA MAMORU , YAGUCHI TATSUYA , YAMAMOTO MASAHIRO , MORI SHINSAKU
IPC分类号： H03H19/00
摘要： PURPOSE:To realize various characteristics by use of one operational amplifier, by controlling a peripheral capacitor group so that the operational amplifier is used for the time division multiplex. CONSTITUTION:A time area for controlling a switch is denoted as I0, I1-I4. A differential variable store SC (switched capacitor) circuit group 30 consists of a capacitor for storing the voltage corresponding to a differential coefficient in each time area, and a switch responding to each time area. An integral feedback SC circuit group 40 stores charge inputted at each time area. The first integral variable store SC circuit group 50 stores the voltage corresponding to charge generated in an output terminal 103. The first addition feedback SC circuit 60 is controlled, for instance, so that the sum total of charge of capacitors C1 -C3 and an input capacitor C0 is stored in a feedback capacitor C4 in the time area I4. Each capacitor is decided from a coefficient obtained by deriving a status equation of Kalman in accordance with a transfer function.

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