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1. 发明授权

US08848430B2 Step soft program for reversible resistivity-switching elements 有权
标题翻译：用于可逆电阻率开关元件的步进软程序
公开(公告)号：US08848430B2
公开(公告)日：2014-09-30
申请号：US12949146
申请日：2010-11-18
申请人： Xiying Chen Costa , Roy Scheuerlein , Abhijit Bandyopadhyay , Brian Le , Li Xiao , Tao Du , Chandrasekhar R. Gorla
发明人： Xiying Chen Costa , Roy Scheuerlein , Abhijit Bandyopadhyay , Brian Le , Li Xiao , Tao Du , Chandrasekhar R. Gorla
IPC分类号： G11C11/00 , G11C14/00 , G11C5/02
CPC分类号： G11C14/00 , G11C5/02 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0076 , G11C2013/0083 , G11C2013/0092 , G11C2213/32
摘要： A method and system for forming, resetting, or setting memory cells is disclosed. One or more programming conditions to apply to a memory cell having a reversible resistivity-switching element may be determined based on its resistance. The determination of one or more programming conditions may also be based on a pre-determined algorithm that may be based on properties of the memory cell. The one or more programming conditions may include a programming voltage and a current limit. For example, the magnitude of the programming voltage may be based on the resistance. As another example, the width of a programming voltage pulse may be based on the resistance. In some embodiments, a current limit used during programming is determined based on the memory cell resistance.
摘要翻译：公开了一种用于形成，复位或设置存储单元的方法和系统。可以基于其电阻来确定应用于具有可逆电阻率开关元件的存储单元的一个或多个编程条件。一个或多个编程条件的确定也可以基于可以基于存储器单元的性质的预定算法。一个或多个编程条件可以包括编程电压和电流限制。例如，编程电压的大小可以基于电阻。作为另一示例，编程电压脉冲的宽度可以基于电阻。在一些实施例中，基于存储单元电阻来确定在编程期间使用的电流限制。

2. 发明申请

US20110205782A1 STEP SOFT PROGRAM FOR REVERSIBLE RESISTIVITY-SWITCHING ELEMENTS 有权
标题翻译：用于可逆电阻开关元件的步骤软件程序
公开(公告)号：US20110205782A1
公开(公告)日：2011-08-25
申请号：US12949146
申请日：2010-11-18
申请人： Xiying Chen Costa , Roy Scheuerlein , Abhijit Bandyopadhyay , Brian Le , Li Xiao , Tao Du , Chandrasekhar R. Gorla
发明人： Xiying Chen Costa , Roy Scheuerlein , Abhijit Bandyopadhyay , Brian Le , Li Xiao , Tao Du , Chandrasekhar R. Gorla
IPC分类号： G11C11/21
CPC分类号： G11C14/00 , G11C5/02 , G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0076 , G11C2013/0083 , G11C2013/0092 , G11C2213/32
摘要： A method and system for forming, resetting, or setting memory cells is disclosed. One or more programming conditions to apply to a memory cell having a reversible resistivity-switching element may be determined based on its resistance. The determination of one or more programming conditions may also be based on a pre-determined algorithm that may be based on properties of the memory cell. The one or more programming conditions may include a programming voltage and a current limit. For example, the magnitude of the programming voltage may be based on the resistance. As another example, the width of a programming voltage pulse may be based on the resistance. In some embodiments, a current limit used during programming is determined based on the memory cell resistance.
摘要翻译：公开了一种用于形成，复位或设置存储单元的方法和系统。可以基于其电阻来确定应用于具有可逆电阻率开关元件的存储单元的一个或多个编程条件。一个或多个编程条件的确定也可以基于可以基于存储器单元的性质的预定算法。一个或多个编程条件可以包括编程电压和电流限制。例如，编程电压的大小可以基于电阻。作为另一示例，编程电压脉冲的宽度可以基于电阻。在一些实施例中，基于存储单元电阻来确定在编程期间使用的电流限制。

3. 发明授权

US08289749B2 Soft forming reversible resistivity-switching element for bipolar switching 有权
标题翻译：用于双极开关的软成型可逆电阻率开关元件
公开(公告)号：US08289749B2
公开(公告)日：2012-10-16
申请号：US12642191
申请日：2009-12-18
申请人： Xiying Chen , Abhijit Bandyopadhyay , Brian Le , Roy Scheuerlein , Li Xiao
发明人： Xiying Chen , Abhijit Bandyopadhyay , Brian Le , Roy Scheuerlein , Li Xiao
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2213/32 , G11C2213/34
摘要： A method and system for forming reversible resistivity-switching elements is described herein. Forming refers to reducing the resistance of the reversible resistivity-switching element, and is generally understood to refer to reducing the resistance for the first time. Prior to forming the reversible resistivity-switching element it may be in a high-resistance state. A first voltage is applied to “partially form” the reversible resistivity-switching element. The first voltage has a first polarity. Partially forming the reversible resistivity-switching element lowers the resistance of the reversible resistivity-switching element. A second voltage that has the opposite polarity as the first is then applied to the reversible resistivity-switching element. Application of the second voltage may further lower the resistance of the reversible resistivity-switching element. Therefore, the second voltage could be considered as completing the forming of the reversible resistivity-switching element.
摘要翻译：本文描述了用于形成可逆电阻率开关元件的方法和系统。形成是指降低可逆电阻率开关元件的电阻，并且通常被理解为指第一次降低电阻。在形成可逆电阻率开关元件之前，它可能处于高电阻状态。施加第一电压以部分地形成可逆电阻率开关元件。第一电压具有第一极性。部分形成可逆电阻率开关元件降低可逆电阻率开关元件的电阻。然后将具有与第一相反极性的第二电压施加到可逆电阻率开关元件。第二电压的施加可以进一步降低可逆电阻率开关元件的电阻。因此，可以将第二电压视为完成可逆电阻率开关元件的形成。

4. 发明申请

US20110085370A1 SOFT FORMING REVERSIBLE RESISTIVITY-SWITCHING ELEMENT FOR BIPOLAR SWITCHING 有权
标题翻译：用于双极开关的软性可逆电阻开关元件
公开(公告)号：US20110085370A1
公开(公告)日：2011-04-14
申请号：US12642191
申请日：2009-12-18
申请人： Xiying Chen , Abhijit Bandyopadhyay , Brian Le , Roy Scheuerlein , Li Xiao
发明人： Xiying Chen , Abhijit Bandyopadhyay , Brian Le , Roy Scheuerlein , Li Xiao
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0007 , G11C13/0064 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2213/32 , G11C2213/34
摘要： A method and system for forming reversible resistivity-switching elements is described herein. Forming refers to reducing the resistance of the reversible resistivity-switching element, and is generally understood to refer to reducing the resistance for the first time. Prior to forming the reversible resistivity-switching element it may be in a high-resistance state. A first voltage is applied to “partially form” the reversible resistivity-switching element. The first voltage has a first polarity. Partially forming the reversible resistivity-switching element lowers the resistance of the reversible resistivity-switching element. A second voltage that has the opposite polarity as the first is then applied to the reversible resistivity-switching element. Application of the second voltage may further lower the resistance of the reversible resistivity-switching element. Therefore, the second voltage could be considered as completing the forming of the reversible resistivity-switching element.
摘要翻译：本文描述了用于形成可逆电阻率开关元件的方法和系统。形成是指降低可逆电阻率开关元件的电阻，并且通常被理解为指第一次降低电阻。在形成可逆电阻率开关元件之前，它可能处于高电阻状态。施加第一电压以“部分地形成”可逆电阻率开关元件。第一电压具有第一极性。部分形成可逆电阻率开关元件降低可逆电阻率开关元件的电阻。然后将具有与第一相反极性的第二电压施加到可逆电阻率开关元件。第二电压的施加可以进一步降低可逆电阻率开关元件的电阻。因此，可以将第二电压视为完成可逆电阻率开关元件的形成。

5. 发明授权

US08385102B2 Alternating bipolar forming voltage for resistivity-switching elements 有权
标题翻译：用于电阻率开关元件的交替双极形成电压
公开(公告)号：US08385102B2
公开(公告)日：2013-02-26
申请号：US12949590
申请日：2010-11-18
申请人： Li Xiao , Abhijit Bandyopadhyay , Tao Du
发明人： Li Xiao , Abhijit Bandyopadhyay , Tao Du
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2213/32 , G11C2213/72
摘要： A method and system for forming reversible resistivity-switching elements is described herein. Forming refers to reducing the resistance of the reversible resistivity-switching element, and may refer to reducing the resistance for the first time. Prior to forming the reversible resistivity-switching element it may be in a high-resistance state. The method may comprise alternating between applying one or more first voltages having a first polarity to the memory cell and applying one or more second voltages having a second polarity that is opposite the first polarity to the memory cell until the reversible resistivity-switching memory element is formed. There may be a rest period between applying the voltages of opposite polarity.
摘要翻译：本文描述了用于形成可逆电阻率开关元件的方法和系统。形成是指降低可逆电阻率开关元件的电阻，并且可以指第一次降低电阻。在形成可逆电阻率开关元件之前，它可能处于高电阻状态。该方法可以包括在向存储器单元施加具有第一极性的一个或多个第一电压并且向存储器单元施加具有与第一极性相反的第二极性的一个或多个第二电压，直到可逆电阻率切换存储元件为形成。在施加相反极性的电压之间可能有一个休息时间。

6. 发明申请

US20110280059A1 ALTERNATING BIPOLAR FORMING VOLTAGE FOR RESISTIVITY-SWITCHING ELEMENTS 有权
标题翻译：替代电阻开关元件的双极形成电压
公开(公告)号：US20110280059A1
公开(公告)日：2011-11-17
申请号：US12949590
申请日：2010-11-18
申请人： Li Xiao , Abhijit Bandyopadhyay , Tao Du
发明人： Li Xiao , Abhijit Bandyopadhyay , Tao Du
IPC分类号： G11C11/21
CPC分类号： G11C13/0007 , G11C13/0069 , G11C2013/0073 , G11C2013/0083 , G11C2013/0092 , G11C2213/32 , G11C2213/72
摘要： A method and system for forming reversible resistivity-switching elements is described herein. Forming refers to reducing the resistance of the reversible resistivity-switching element, and may refer to reducing the resistance for the first time. Prior to forming the reversible resistivity-switching element it may be in a high-resistance state. The method may comprise alternating between applying one or more first voltages having a first polarity to the memory cell and applying one or more second voltages having a second polarity that is opposite the first polarity to the memory cell until the reversible resistivity-switching memory element is formed. There may be a rest period between applying the voltages of opposite polarity.
摘要翻译：本文描述了用于形成可逆电阻率开关元件的方法和系统。形成是指降低可逆电阻率开关元件的电阻，并且可以指第一次降低电阻。在形成可逆电阻率开关元件之前，它可能处于高电阻状态。该方法可以包括在向存储器单元施加具有第一极性的一个或多个第一电压并且向存储器单元施加具有与第一极性相反的第二极性的一个或多个第二电压，直到可逆电阻率切换存储元件为形成。在施加相反极性的电压之间可能有一个休息时间。

7. 发明申请

US20060221758A1 TRANSISTOR LAYOUT CONFIGURATION FOR TIGHT-PITCHED MEMORY ARRAY LINES 有权
标题翻译：用于紧凑的内存阵列的晶体管布局配置
公开(公告)号：US20060221758A1
公开(公告)日：2006-10-05
申请号：US11420787
申请日：2006-05-29
申请人： Christopher Petti , Roy Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
发明人： Christopher Petti , Roy Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C8/08 , H01L27/0207 , H01L27/0688 , H01L27/10894 , H01L27/10897
摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line. In certain embodiments, a respective plurality of complementary array line driver circuits is disposed on each side of a connection area between adjacent memory blocks, and each such driver circuit is responsive to a single driver input node.
摘要翻译：多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管线。在某些实施例中，相应的多个互补阵列线驱动器电路设置在相邻存储块之间的连接区域的每一侧上，并且每个这样的驱动器电路响应于单个驱动器输入节点。

8. 发明授权

US08624293B2 Carbon/tunneling-barrier/carbon diode 有权
标题翻译：碳/隧道势垒/碳二极管
公开(公告)号：US08624293B2
公开(公告)日：2014-01-07
申请号：US12639840
申请日：2009-12-16
申请人： Abhijit Bandyopadhyay , Franz Kreupl , Andrei Mihnea , Li Xiao
发明人： Abhijit Bandyopadhyay , Franz Kreupl , Andrei Mihnea , Li Xiao
IPC分类号： H01L29/66
CPC分类号： H01L45/00 , H01L27/2418 , H01L27/2463 , H01L29/16 , H01L29/88
摘要： A carbon/tunneling-barrier/carbon diode and method for forming the same are disclosed. The carbon/tunneling-barrier/carbon may be used as a steering element in a memory array. Each memory cell in the memory array may include a reversible resistivity-switching element and a carbon/tunneling-barrier/carbon diode as the steering element. The tunneling-barrier may include a semiconductor or an insulator. Thus, the diode may be a carbon/semiconductor/carbon diode. The semiconductor in the diode may be intrinsic or doped. The semiconductor may be depleted when the diode is under equilibrium conditions. For example, the semiconductor may be lightly doped such that the depletion region extends from one end of the semiconductor region to the other end. The diode may be a carbon/insulator/carbon diode.
摘要翻译：公开了一种碳/隧道势垒/碳二极管及其形成方法。碳/隧道势垒/碳可以用作存储器阵列中的转向元件。存储器阵列中的每个存储单元可以包括可逆电阻率开关元件和作为转向元件的碳/隧道势垒/碳二极管。隧道势垒可以包括半导体或绝缘体。因此，二极管可以是碳/半导体/碳二极管。二极管中的半导体可以是固有的或掺杂的。当二极管处于平衡条件下时，半导体可能耗尽。例如，半导体可以被轻掺杂，使得耗尽区从半导体区的一端延伸到另一端。二极管可以是碳/绝缘体/碳二极管。

9. 发明授权

US08520425B2 Resistive random access memory with low current operation 有权
标题翻译：具有低电流运行的电阻式随机存取存储器
公开(公告)号：US08520425B2
公开(公告)日：2013-08-27
申请号：US13424131
申请日：2012-03-19
申请人： Li Xiao , Chandu Gorla , Abhijit Bandyopadhyay , Andrei Mihnea
发明人： Li Xiao , Chandu Gorla , Abhijit Bandyopadhyay , Andrei Mihnea
IPC分类号： G11C11/00 , G11C13/0002
CPC分类号： G11C13/0007 , G11C5/02 , G11C8/10 , G11C13/0023 , G11C13/0069 , G11C13/0097 , G11C2013/0073 , G11C2013/0083 , G11C2213/32 , G11C2213/33 , G11C2213/71 , G11C2213/72 , G11C2213/76 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/122 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： A memory cell in a 3-D read and write memory device has two bipolar resistance-switching layers with different respective switching currents. A low current resistance-switching layer can be switched in set and reset processes while a high current resistance-switching layer remains in a reset state and acts as a protection resistor to prevent excessively high currents on the low current resistance-switching layer. The low and high current resistance-switching layers can be of the same material such as a metal oxide, where the layers differ in terms of thickness, doping, leakiness, metal richness or other variables. Or, the low and high current resistance-switching layers can be of different materials, having one or more layers each. The high current resistance-switching layer can have a switching current which is greater than a switching current of the low current resistance-switching layer by a factor of at least 1.5 or 2.0, for instance.
摘要翻译： 3-D读写存储器件中的存储单元具有两个具有不同开关电流的双极性电阻切换层。低电流电阻切换层可以在置位和复位过程中被切换，而高电流电阻切换层保持复位状态，并且作为保护电阻来防止低电流电阻切换层上的过大电流。低电流和高电流电阻切换层可以是相同的材料，例如金属氧化物，其中层的厚度，掺杂，泄漏，金属浓度等变化不同。或者，低电流和高电流电阻切换层可以是不同的材料，每个具有一个或多个层。高电流电阻切换层例如可以具有比低电流电阻切换层的开关电流大至少1.5或2.0的开关电流。

10. 发明申请

US20110140064A1 CARBON/TUNNELING-BARRIER/CARBON DIODE 有权
标题翻译：碳/隧道障碍物/碳二极管
公开(公告)号：US20110140064A1
公开(公告)日：2011-06-16
申请号：US12639840
申请日：2009-12-16
申请人： Abhijit Bandyopadhyay , Franz Kreupl , Andrei Mihnea , Li Xiao
发明人： Abhijit Bandyopadhyay , Franz Kreupl , Andrei Mihnea , Li Xiao
IPC分类号： H01L47/00 , H01L29/885 , H01L21/04 , H01L29/861
CPC分类号： H01L45/00 , H01L27/2418 , H01L27/2463 , H01L29/16 , H01L29/88
摘要： A carbon/tunneling-barrier/carbon diode and method for forming the same are disclosed. The carbon/tunneling-barrier/carbon may be used as a steering element in a memory array. Each memory cell in the memory array may include a reversible resistivity-switching element and a carbon/tunneling-barrier/carbon diode as the steering element. The tunneling-barrier may include a semiconductor or an insulator. Thus, the diode may be a carbon/semiconductor/carbon diode. The semiconductor in the diode may be intrinsic or doped. The semiconductor may be depleted when the diode is under equilibrium conditions. For example, the semiconductor may be lightly doped such that the depletion region extends from one end of the semiconductor region to the other end. The diode may be a carbon/insulator/carbon diode.
摘要翻译：公开了一种碳/隧道势垒/碳二极管及其形成方法。碳/隧道势垒/碳可以用作存储器阵列中的转向元件。存储器阵列中的每个存储单元可以包括可逆电阻率开关元件和作为转向元件的碳/隧道势垒/碳二极管。隧道势垒可以包括半导体或绝缘体。因此，二极管可以是碳/半导体/碳二极管。二极管中的半导体可以是固有的或掺杂的。当二极管处于平衡条件下时，半导体可能耗尽。例如，半导体可以被轻掺杂，使得耗尽区从半导体区的一端延伸到另一端。二极管可以是碳/绝缘体/碳二极管。

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