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    • 3. 发明授权
    • Adaptive equalization employing pattern recognition
    • 使用模式识别的自适应均衡
    • US08045609B2
    • 2011-10-25
    • US12221003
    • 2008-07-30
    • Xingdong DaiGeoffrey ZhangMax OlsenDwight Daugherty
    • Xingdong DaiGeoffrey ZhangMax OlsenDwight Daugherty
    • H03H7/30
    • H04L25/03019
    • In described embodiments, an adaptive equalizer employed by a receiver in a communication channel, such as Fiber Channel, employs pattern recognition. When a repeating pattern, such as an IDLE or ARBFF pattern, is employed by a standard to, for example, maintain a communication link, an equalizer of the receiver might adaptively set its equalizer parameters based on characteristics of the signal energy of the repeating pattern rather than adaptively set its equalizer parameters based on characteristics of the signal energy of generally random user data carried on the link. Pattern recognition by the receiver allows for maintaining adaptive equalizer parameters at settings preferred for data detection of the typical random data, improving data detection performance of the receiver when the channel transitions from a preset or synchronization repeating pattern to a user random data pattern.
    • 在所描述的实施例中,由诸如光纤通道的通信信道中的接收机使用的自适应均衡器使用模式识别。 当诸如空闲或ARBFF模式的重复模式被标准采用以例如维持通信链路时,接收机的均衡器可以基于重复模式的信号能量的特性来自适应地设置其均衡器参数 而不是基于在链路上携带的一般随机用户数据的信号能量的特性自适应地设置其均衡器参数。 接收机的模式识别允许在优选用于典型随机数据的数据检测的设置下维持自适应均衡器参数,当信道从预设或同步重复模式转换到用户随机数据模式时,提高接收机的数据检测性能。
    • 5. 发明申请
    • Offset test pattern apparatus and method
    • 偏移测试图案设备和方法
    • US20060253757A1
    • 2006-11-09
    • US11121164
    • 2005-05-03
    • Robert BrinkJames HofmannMax OlsenGary SchiesslerLane Smith
    • Robert BrinkJames HofmannMax OlsenGary SchiesslerLane Smith
    • G06F11/00G01R31/28
    • H04L1/244
    • Communications equipment can be tested using a test pattern encapsulated within a frame, and offsetting the test pattern in each successive frame. In equipment having a number of data latches receiving serial input, the introduction of the offset allows each latch, over time, to be exposed to the same pattern as the other latches. That is, the latches “see” different portions of the pattern at a given time, but over time, each can be exposed to the full pattern. Otherwise, each latch would “see” its own static pattern, different from the other latches, but the same over time with respect to itself. The offset can enhance diagnostic capabilities of the test pattern.
    • 可以使用封装在帧内的测试图案来测试通信设备,并且在每个连续帧中抵消测试模式。 在具有接收串行输入的多个数据锁存器的设备中,引入偏移允许每个锁存器随时间暴露于与其他锁存器相同的模式。 也就是说,锁定器在给定时间“看到”图案的不同部分,但是随着时间的推移,每个可以暴露于完整图案。 否则,每个锁存器将“看到”其自己的静态模式,与其他锁存器不同,但是相对于自身而言随着时间的推移相同。 该偏移可以增强测试图案的诊断功能。
    • 6. 发明申请
    • Pseudo asynchronous serializer deserializer (SERDES) testing
    • 伪异步串行器解串器(SERDES)测试
    • US20070014342A1
    • 2007-01-18
    • US11181286
    • 2005-07-14
    • Vladimir SindalovskyLane SmithRonald FreymanMax Olsen
    • Vladimir SindalovskyLane SmithRonald FreymanMax Olsen
    • H04B17/00
    • G01R31/31715
    • The various embodiments of the invention provide an apparatus, system and method of asynchronous testing a serializer and deserializer data communication apparatus (SERDES) for determining frequency and phase locking to pseudo asynchronous input data having a continual phase offset. An exemplary apparatus includes a data sampler adapted to sample input serial data and to provide output data; a controlled tap delay with a selected tap having a phase offset from the input serial data, in which the selected tap is selectively coupleable to the data sampler to provide pseudo asynchronous input serial data; a first variable delay control adapted to delay a reference frequency provided to the controlled tap delay in response to the pseudo asynchronous input serial data; and a second delay control adapted to adjust the plurality of taps in response to the pseudo asynchronous input serial data. In additional embodiments, the pseudo asynchronous input serial data is provided from an interpolated phase from at least two selected taps.
    • 本发明的各种实施例提供了用于确定频率和相位锁定到具有连续相位偏移的伪异步输入数据的串行器和解串器数据通信装置(SERDES)的异步测试的装置,系统和方法。 示例性装置包括适于对输入串行数据进行采样并提供输出数据的数据采样器; 具有与输入串行数据相位偏移的所选抽头的受控抽头延迟,其中所选择的抽头选择性地耦合到数据采样器以提供伪异步输入串行数据; 第一可变延迟控制器,其适于响应于所述伪异步输入串行数据延迟提供给受控抽头延迟的参考频率; 以及适于响应于所述伪异步输入串行数据来调整所述多个抽头的第二延迟控制。 在另外的实施例中,伪异步输入串行数据从来自至少两个选择的抽头的内插相位提供。
    • 7. 发明申请
    • Frequency-lock detector
    • US20060176992A1
    • 2006-08-10
    • US11053365
    • 2005-02-08
    • Xingdong DiaMax OlsenLane Smith
    • Xingdong DiaMax OlsenLane Smith
    • H04L7/02
    • H04L7/033H03L7/095
    • A frequency-lock detector (FLD) adapted to register more than one target count per period of a target clock signal to generate a count value related to a frequency difference between the target clock signal and a reference clock signal. In various embodiments of the invention, this count registration is implemented by multiplying the target clock signal, discerning two or more phases of a signal, and/or organizing a count pipeline. In a representative embodiment, an FLD of the invention has a counter circuit and a control circuit. The counter circuit has (i) a frequency multiplier adapted to multiply the frequency of the target clock signal to generate a multiplied signal, (ii) two target counters adapted to register counts based on occurrences of two different phases of the accelerated signal to generate two auxiliary numbers, and (iii) a multiplexer adapted to select an appropriate one of the auxiliary numbers as the count value related to the frequency difference. The control circuit has a reference counter adapted to control, based on the reference clock signal, the count registration in the target counters and the value selection in the multiplexer.