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1. 发明授权

US08559580B2 Asynchronous calibration for eye diagram generation 有权
标题翻译：眼图生成的异步校准
公开(公告)号：US08559580B2
公开(公告)日：2013-10-15
申请号：US12494771
申请日：2009-06-30
申请人： Xingdong Dai , Dwight David Daugherty , Max J. Olsen , Lane A. Smith , Geoffrey Zhang
发明人： Xingdong Dai , Dwight David Daugherty , Max J. Olsen , Lane A. Smith , Geoffrey Zhang
IPC分类号： H04L7/00 , H04L25/00 , H04L25/40
CPC分类号： H04L1/20
摘要： Techniques are disclosed for asynchronous calibration for eye diagram generation. For example, a method for calibrating a process for generating a data eye associated with a received signal comprises the following steps. Samples of the received signal are obtained for a first unit interval using a first data latch and a roaming latch. A delay offset is determined between the first data latch and the roaming latch by comparing at least one sample obtained using the first data latch and at least one sample obtained using the roaming latch, wherein the delay offset determined by the comparison is used to calibrate the process for generating the data eye associated with the received signal. A similar comparison may be done for a second data latch and used to calibrate the process. The method is able to find the accurate position of each data latch with respect to the roaming latch so as to improve the accuracy of data decoding in a digital receiver, i.e., provide receiver optimization.
摘要翻译：公开了用于眼图生成的异步校准的技术。例如，用于校准与接收信号相关联的用于生成数据眼的处理的方法包括以下步骤。使用第一数据锁存器和漫游锁存器，以第一单位间隔获得接收信号的样本。通过比较使用第一数据锁存器获得的至少一个样本和使用漫游锁存器获得的至少一个样本，在第一数据锁存器和漫游锁存器之间确定延迟偏移，其中由比较确定的延迟偏移用于校准用于产生与接收信号相关联的数据眼的过程。可以对第二数据锁存器进行类似的比较，并用于校准该过程。该方法能够找到每个数据锁存器相对于漫游锁存器的准确位置，以提高数字接收机中数据解码的准确度，即提供接收机优化。

2. 发明申请

US20100329318A1 Asynchronous Calibration for Eye Diagram Generation 有权
标题翻译：用于眼图生成的异步校准
公开(公告)号：US20100329318A1
公开(公告)日：2010-12-30
申请号：US12494771
申请日：2009-06-30
申请人： Xingdong Dai , Dwight David Daugherty , Max J. Olsen , Lane A. Smith , Geoffrey Zhang
发明人： Xingdong Dai , Dwight David Daugherty , Max J. Olsen , Lane A. Smith , Geoffrey Zhang
IPC分类号： H04B17/00
CPC分类号： H04L1/20
摘要： Techniques are disclosed for asynchronous calibration for eye diagram generation. For example, a method for calibrating a process for generating a data eye associated with a received signal comprises the following steps. Samples of the received signal are obtained for a first unit interval using a first data latch and a roaming latch. A delay offset is determined between the first data latch and the roaming latch by comparing at least one sample obtained using the first data latch and at least one sample obtained using the roaming latch, wherein the delay offset determined by the comparison is used to calibrate the process for generating the data eye associated with the received signal. A similar comparison may be done for a second data latch and used to calibrate the process. The method is able to find the accurate position of each data latch with respect to the roaming latch so as to improve the accuracy of data decoding in a digital receiver, i.e., provide receiver optimization.
摘要翻译：公开了用于眼图生成的异步校准的技术。例如，用于校准与接收信号相关联的用于生成数据眼的处理的方法包括以下步骤。使用第一数据锁存器和漫游锁存器，以第一单位间隔获得接收信号的样本。通过比较使用第一数据锁存器获得的至少一个样本和使用漫游锁存器获得的至少一个样本，在第一数据锁存器和漫游锁存器之间确定延迟偏移，其中由比较确定的延迟偏移用于校准用于产生与接收信号相关联的数据眼的过程。可以对第二数据锁存器进行类似的比较，并用于校准该过程。该方法能够找到每个数据锁存器相对于漫游锁存器的准确位置，以提高数字接收机中数据解码的准确度，即提供接收机优化。

3. 发明授权

US07489754B2 Frequency-lock detector 失效
标题翻译：锁频检测器
公开(公告)号：US07489754B2
公开(公告)日：2009-02-10
申请号：US11053365
申请日：2005-02-08
申请人： Xingdong Dai , Max J. Olsen , Lane A. Smith
发明人： Xingdong Dai , Max J. Olsen , Lane A. Smith
IPC分类号： H04L7/02
CPC分类号： H04L7/033 , H03L7/095
摘要： A frequency-lock detector (FLD) adapted to register more than one target count per period of a target clock signal to generate a count value related to a frequency difference between the target clock signal and a reference clock signal. In various embodiments of the invention, this count registration is implemented by multiplying the target clock signal, discerning two or more phases of a signal, and/or organizing a count pipeline. In a representative embodiment, an FLD of the invention has a counter circuit and a control circuit. The counter circuit has (i) a frequency multiplier adapted to multiply the frequency of the target clock signal to generate a multiplied signal, (ii) two target counters adapted to register counts based on occurrences of two different phases of the accelerated signal to generate two auxiliary numbers, and (iii) a multiplexer adapted to select an appropriate one of the auxiliary numbers as the count value related to the frequency difference. The control circuit has a reference counter adapted to control, based on the reference clock signal, the count registration in the target counters and the value selection in the multiplexer.
摘要翻译：一种频率锁定检测器（FLD），适于在目标时钟信号的每个周期寄存多于一个目标计数，以产生与目标时钟信号和参考时钟信号之间的频率差相关的计数值。在本发明的各种实施例中，通过对目标时钟信号进行乘法，辨别信号的两个或多个相位和/或组织计数流水线来实现该计数登记。在代表性的实施例中，本发明的FLD具有计数器电路和控制电路。计数器电路具有（i）适于乘以目标时钟信号的频率以产生相乘的信号的倍频器，（ii）适于基于加速信号的两个不同相位的出现来寄存计数的两个目标计数器，以产生两个辅助号码，以及（iii）适合于选择适当的一个辅助号码作为与频率差有关的计数值的多路复用器。该控制电路具有一个参考计数器，该参考计数器适于基于参考时钟信号控制目标计数器中的计数注册和多路复用器中的值选择。

4. 发明授权

US08428195B2 Methods and apparatus for detecting and decoding adaptive equalization training frames 有权
标题翻译：用于检测和解码自适应均衡训练帧的方法和装置
公开(公告)号：US08428195B2
公开(公告)日：2013-04-23
申请号：US11967463
申请日：2007-12-31
申请人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
发明人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
IPC分类号： H04L27/06
CPC分类号： H04L27/01 , H04L7/0066 , H04L7/0083 , H04L25/4904
摘要： Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.
摘要翻译：提供了用于检测和解码自适应均衡训练帧（具有包括二进制和二进制零序列的帧标记）的方法和装置。通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时，检测所述帧标记。使用框架制造商的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。

5. 发明申请

US20090168862A1 Methods and Apparatus for Detecting and Decoding Adaptive Equalization Training Frames 有权
标题翻译：用于检测和解码自适应均衡训练帧的方法和装置
公开(公告)号：US20090168862A1
公开(公告)日：2009-07-02
申请号：US11967463
申请日：2007-12-31
申请人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
发明人： Yasser Ahmed , Xingdong Dai , Mohammad S. Mobin , Lane A. Smith
IPC分类号： H04L27/01
CPC分类号： H04L27/01 , H04L7/0066 , H04L7/0083 , H04L25/4904
摘要： Methods and apparatus are provided for detecting and decoding adaptive equalization training frames (having a frame marker comprised of a string of binary ones and binary zeroes). Training frames are detected by shifting the received data; inserting at least one binary value at one end of the shifted received data to generate a modified version of the received data; applying a logic function to the received data and the modified version of the received data that identifies when corresponding bit positions have different values; and detecting the frame marker when an output of the logic function has a first binary value in an approximate middle of a string of a second binary value. The training frames are decoded using a distance between the approximate center of the frame maker and a predefined binary value in an output of the logic function.
摘要翻译：提供了用于检测和解码自适应均衡训练帧（具有包括二进制和二进制零序列的帧标记）的方法和装置。通过移位接收到的数据来检测训练帧; 在移位的接收数据的一端插入至少一个二进制值以产生所接收数据的修改版本; 对所接收的数据应用逻辑功能以及当对应的位位置具有不同值时识别的接收数据的修改版本; 以及当所述逻辑功能的输出在第二二进制值的字符串的大致中间具有第一二进制值时，检测所述帧标记。使用框架制造商的近似中心之间的距离和逻辑功能的输出中的预定二进制值对训练帧进行解码。

6. 发明授权

US07447965B2 Offset test pattern apparatus and method 失效
标题翻译：偏移测试图案设备和方法
公开(公告)号：US07447965B2
公开(公告)日：2008-11-04
申请号：US11121164
申请日：2005-05-03
申请人： Robert D. Brink , James Walter Hofmann, Jr. , Max J. Olsen , Gary E. Schiessler , Lane A. Smith
发明人： Robert D. Brink , James Walter Hofmann, Jr. , Max J. Olsen , Gary E. Schiessler , Lane A. Smith
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： H04L1/244
摘要： Communications equipment can be tested using a test pattern encapsulated within a frame, and offsetting the test pattern in each successive frame. In equipment having a number of data latches receiving serial input, the introduction of the offset allows each latch, over time, to be exposed to the same pattern as the other latches. That is, the latches “see” different portions of the pattern at a given time, but over time, each can be exposed to the full pattern. Otherwise, each latch would “see” its own static pattern, different from the other latches, but the same over time with respect to itself. The offset can enhance diagnostic capabilities of the test pattern.
摘要翻译：可以使用封装在帧内的测试图案来测试通信设备，并且在每个连续帧中抵消测试模式。在具有接收串行输入的多个数据锁存器的设备中，引入偏移允许每个锁存器随时间暴露于与其他锁存器相同的模式。也就是说，锁定器在给定时间“看到”图案的不同部分，但是随着时间的推移，每个可以暴露于完整图案。否则，每个锁存器将“看到”其自己的静态模式，与其他锁存器不同，但是相对于自身而言随着时间的推移相同。该偏移可以增强测试图案的诊断功能。

7. 发明授权

US07272756B2 Exploitive test pattern apparatus and method 失效
标题翻译：利用测试图案设备和方法
公开(公告)号：US07272756B2
公开(公告)日：2007-09-18
申请号：US11121152
申请日：2005-05-03
申请人： Robert D. Brink , James Walter Hofmann, Jr. , Max J. Olsen , Gary E. Schiessler , Lane A. Smith
发明人： Robert D. Brink , James Walter Hofmann, Jr. , Max J. Olsen , Gary E. Schiessler , Lane A. Smith
IPC分类号： G01R31/28
CPC分类号： H04L1/244 , H04L43/50
摘要： Communications equipment can be tested using a test pattern that is modified compared to, and more exploitive than, a standard test pattern. Test patterns can be employed that have lengthened or shortened consecutive identical digit (CID) portions, or that have lengthened or shortened pseudo random bit sequence (PRBS) portions. In some cases, PRBS polynomials are not re-seeded after each CID. Further, different order polynomials can be employed for different applications. Exemplary applications can include test equipment and built-in self-test capability for integrated circuits.
摘要翻译：通信设备可以使用与标准测试模式相比修改的测试模式进行测试，并且比标准测试模式更具有潜力。可以采用具有延长或缩短连续相同数字（CID）部分或具有延长或缩短的伪随机位序列（PRBS）部分的测试模式。在某些情况下，在每个CID之后，PRBS多项式不再重播。此外，不同的阶多项式可以用于不同的应用。示例性应用可以包括测试设备和用于集成电路的内置自检能力。

8. 发明申请

US20090168940A1 Methods and Apparatus for Improved Jitter Tolerance in an SFP Limit Amplified Signal 失效
标题翻译：用于改善SFP限幅放大信号中抖动容限的方法和装置
公开(公告)号：US20090168940A1
公开(公告)日：2009-07-02
申请号：US11967602
申请日：2007-12-31
申请人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
发明人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
IPC分类号： H04L7/00
CPC分类号： H04B10/6972
摘要： Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i.e., rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter.
摘要翻译：提供了用于改善SFP限幅放大信号中的抖动容限的方法和装置。在通信接收机中通过将接收到的信号施加到SFP限幅放大器来提高抖动容差; 并将SFP限幅放大器的输出施加到低通滤波器以提高抖动容限。低通滤波器可选择地将可编程量的衰减应用于输出的高频分量。低通滤波器转换速率控制（即旋转）接收信号的数据眼表示，以沿着时间轴增加数据眼睛表示。可以通过将低通滤波器的输出施加到全通滤波器来可选地改善接收信号的噪声容限。压摆率控制器可以评估数据眼统计量，以确定低通滤波器的设置。

9. 发明授权

US08040984B2 Methods and apparatus for improved jitter tolerance in an SFP limit amplified signal 失效
标题翻译：用于改善SFP限幅放大信号中抖动容限的方法和装置
公开(公告)号：US08040984B2
公开(公告)日：2011-10-18
申请号：US11967602
申请日：2007-12-31
申请人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
发明人： Pervez M. Aziz , Adam B. Healey , Mohammad S. Mobin , Gary E. Schiessler , Gregory W. Sheets , Lane A. Smith , Paul H. Tracy , Geoffrey Zhang
IPC分类号： H04L25/08 , H04L7/10 , H04L7/00
CPC分类号： H04B10/6972
摘要： Methods and apparatus are provided for improving the jitter tolerance in an SFP limit amplified signal. Jitter tolerance is improved in a communications receiver by applying a received signal to an SFP limiting amplifier; and applying an output of the SFP limiting amplifier to a low pass filter to improve the jitter tolerance. The low pass filter optionally applies a programmable amount of attenuation to high frequency components of the output. The low pass filter slew rate controls (i.e., rotates) a data eye representation of the received signal to increase the data eye representation along a time axis. The noise margin of the received signal can optionally be improved by applying an output of the low pass filter to an all pass filter. A slew rate controller can evaluate the data eye statistics to determine a setting for the low pass filter.
摘要翻译：提供了用于改善SFP限幅放大信号中的抖动容限的方法和装置。在通信接收机中通过将接收到的信号施加到SFP限幅放大器来提高抖动容差; 并将SFP限幅放大器的输出施加到低通滤波器以提高抖动容限。低通滤波器可选择地将可编程量的衰减应用于输出的高频分量。低通滤波器转换速率控制（即旋转）接收信号的数据眼表示，以沿着时间轴增加数据眼睛表示。可以通过将低通滤波器的输出施加到全通滤波器来可选地改善接收信号的噪声容限。压摆率控制器可以评估数据眼统计量，以确定低通滤波器的设置。

10. 发明申请

US20140068122A1 METHOD, SYSTEM AND PROCESSOR-READABLE MEDIA FOR ASCERTAINING A MAXIMUM NUMBER OF CONTIGUOUS BITS OF LOGICAL ONES OR ZEROS WITHIN A PARALLEL WORD OF ARBITRARY WIDTH 审中-公开
标题翻译：方法，系统和处理器可读介质，用于排除最大数目的逻辑角或零点的平行字，
公开(公告)号：US20140068122A1
公开(公告)日：2014-03-06
申请号：US13604048
申请日：2012-09-05
申请人： Qiao Shen , Samuel Khoo , Wen Zhu , Lane A. Smith
发明人： Qiao Shen , Samuel Khoo , Wen Zhu , Lane A. Smith
IPC分类号： G06F13/14
CPC分类号： G06F13/4204 , Y02D10/14 , Y02D10/151
摘要： Methods, systems and processor-readable media for reducing the width of a logical comparison. A width of a logical comparison based on a previous result generated can be recursively reduced from a data stream and a maximum count of consecutive ones or consecutive zeros determined from the serial data stream based on a priority encoder within a single clock cycle in order to avoid a use of complex functions. In this manner, the maximum number of the consecutive ones or the consecutive zeros in a parallel word bus within the single dock cycle can be ascertained.
摘要翻译：用于减少逻辑比较宽度的方法，系统和处理器可读介质。基于生成的先前结果的逻辑比较的宽度可以从单个时钟周期内的基于优先级编码器的数据流和从串行数据流确定的连续零的最大计数递归地减少，以避免使用复杂的功能。以这种方式，可以确定单个码头周期内的并行字总线中的连续零或连续零的最大数目。

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