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1. 发明申请

WO2014028066A1 FLEXIBLE SIZED DIE FOR USE IN MULTI-DIE INTEGRATED CIRCUIT 审中-公开
标题翻译：灵活尺寸的DIE用于多集成电路
公开(公告)号：WO2014028066A1
公开(公告)日：2014-02-20
申请号：PCT/US2013/036610
申请日：2013-04-15
申请人： XILINX, INC.
发明人： CAMAROTA, Rafael, C.
IPC分类号： H01L25/065 , H01L23/14 , H01L21/66 , G01R31/28
CPC分类号： G01R31/28 , H01L21/78 , H01L22/32 , H01L23/145 , H01L23/147 , H01L23/49827 , H01L25/0652 , H01L25/0655 , H01L2224/13116 , H01L2224/13139 , H01L2224/13147 , H01L2224/16145 , H01L2224/16225 , H01L2224/32225 , H01L2224/48227 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2924/14 , H01L2924/14253 , H01L2924/1432 , H01L2924/1433 , H01L2924/1434 , H01L2924/1435 , H01L2924/15192 , H01L2924/15311 , H01L2924/157 , H01L2924/15788 , H01L2924/0105
摘要： An integrated circuit (IC) structure (100) can include a first die (110) and a second die (115). The second die can include a first base unit (120) and a second base unit (130). Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer (105). The interposer includes a first plurality of inter-die wires (215A) coupling the first die to the first base unit, a second plurality of inter-die wires (215C) coupling the first die to the second base unit, and a third plurality of inter-die wires (215D) coupling the first base unit to the second base unit. In some embodiments, the first and second base units are identical.
摘要翻译：集成电路（IC）结构（100）可以包括第一管芯（110）和第二管芯（115）。第二模具可以包括第一基座单元（120）和第二基座单元（130）。第一基座单元和第二基座单元中的每一个是独立的，并且在第二模具内的第一基座单元和第二基座单元之间没有信号通过。 IC结构可以包括插入件（105）。插入器包括将第一管芯耦合到第一基板单元的第一多个管芯间线（215A），将第一管芯连接到第二基座单元的第二多个管芯间线（215C），以及第三多个管芯将第一基座单元连接到第二基座单元的芯片间导线（215D）。在一些实施例中，第一和第二基座单元是相同的。

2. 发明申请

WO2018026511A8 HETEROGENEOUS BALL PATTERN PACKAGE 审中-公开
公开(公告)号：WO2018026511A8
公开(公告)日：2018-02-08
申请号：PCT/US2017/042649
申请日：2017-07-18
申请人： XILINX, INC.
发明人： CAMAROTA, Rafael, C.
IPC分类号： H01L23/498 , H01L23/528
摘要： Methods and apparatus are described for strategically arranging conductive elements (e.g., solder balls (210, 302)) of an integrated circuit (IC) package (200, 320, 340) (and the corresponding conductive pads (401 ) of a circuit board for electrical connection with the IC package) using a plurality of different pitches. One example integrated circuit (IC) package (320, 340) generally includes an integrated circuit die (204) and an arrangement of electrically conductive elements coupled to the integrated circuit die. In at least one region (326, 328) of the arrangement, the conductive elements are disposed with a first pitch in a first dimension (301, 303) of the arrangement and with a second pitch in a second dimension (303, 301 ) of the arrangement, and the second pitch is different from the first pitch. The pitch of a given region may be based on mechanical, PCB routing, and/or signal integrity considerations.

3. 发明申请

WO2015016973A1 DUAL PORT MEMORY CELL 审中-公开
标题翻译：双端口存储单元
公开(公告)号：WO2015016973A1
公开(公告)日：2015-02-05
申请号：PCT/US2014/021347
申请日：2014-03-06
申请人： XILINX, INC.
发明人： CAMAROTA, Rafael, C.
IPC分类号： H01L27/11 , G11C8/16 , H01L29/78 , H01L27/088
CPC分类号： H01L21/8238 , G11C8/16 , H01L27/0886 , H01L27/1104 , H01L29/785
摘要： A multi-port memory cell is disclosed that includes first (P1+N1 ) and second (P2+N2) cross-coupled inverter circuits. The input node (150/180) of each inverter circuit is coupled to the output node (180/150) of the other inverter circuit to receive the inverted output of the other inverter circuit. The multi-port memory cell includes a first pair of access transistors of a first type (P3, P4), each coupled to the input node (150, 180) of a respective one of the first and second inverter circuits. The multi-port memory cell also includes a second pair of access transistors (N3, N4) of a second type, each coupled to the input node (150, 180) of a respective one of the first and second inverter circuits. The multi- port cell exhibits advantages in layout compactness and SEU tolerance.
摘要翻译：公开了一种多端口存储单元，其包括第一（P1 + N1）和第二（P2 + N2）交叉耦合的反相器电路。每个逆变器电路的输入节点（150/180）耦合到另一个逆变器电路的输出节点（180/150），以接收另一个逆变器电路的反相输出。多端口存储单元包括第一类型（P3，P4）的第一对存取晶体管，每一个都连接到第一和第二反相器电路中的相应一个的输入节点（150,180）。多端口存储单元还包括第二类型的第二对存取晶体管（N3，N4），每一个耦合到第一和第二反相器电路中的相应一个的输入节点（150,180）。多端口单元在布局紧凑性和SEU容差方面具有优势。

4. 发明申请

WO2015002681A1 MONOLITHIC INTEGRATED CIRCUIT DIE HAVING MODULAR DIE REGIONS STITCHED TOGETHER 审中-公开
标题翻译：具有模块化地区的单片集成电路
公开(公告)号：WO2015002681A1
公开(公告)日：2015-01-08
申请号：PCT/US2014/033526
申请日：2014-04-09
申请人： XILINX, INC.
发明人： CAMAROTA, Rafael, C.
IPC分类号： H03K19/177 , G01R31/3185 , G01R31/317
CPC分类号： G01R31/26 , G01R31/31721 , G01R31/31723 , G01R31/318505 , G01R31/318516 , H03K19/17728 , H03K19/1774 , H03K19/17772 , H03K19/17788
摘要： An apparatus for a monolithic integrated circuit die (200) is disclosed. In this apparatus, the monolithic integrated circuit die (200) has a plurality of modular die regions (211, 212). The modular die regions (211, 212) respectively have a plurality of power distribution networks (271, 272) for independently powering each of the modular die regions. Each adjacent pair of the modular die regions (211, 212) is stitched together with a respective plurality of metal lines (260, 301 -304, 514, 524).
摘要翻译：公开了一种用于单片集成电路管芯（200）的装置。在该装置中，单体集成电路管芯（200）具有多个模块管芯区域（211,212）。模块化管芯区域（211,212）分别具有用于独立地为每个模块管芯区域供电的多个配电网络（271,272）。每个相邻的一对模块模具区域（211,212）与相应的多个金属线（260,301,304,514,524）缝合在一起。

5. 发明申请

WO2018034787A1 STANDALONE INTERFACE FOR STACKED SILICON INTERCONNECT (SSI) TECHNOLOGY INTEGRATION 审中-公开
标题翻译： STACKALONE INTERFACE用于堆叠硅互连（SSI）技术集成
公开(公告)号：WO2018034787A1
公开(公告)日：2018-02-22
申请号：PCT/US2017/043096
申请日：2017-07-20
申请人： XILINX, INC.
发明人： CAMAROTA, Rafael, C. , AHMAD, Sagheer , NEWMAN, Martin
IPC分类号： H01L23/498 , H01L23/525 , H01L23/538 , H01L25/065 , H01L25/16 , H01L25/18
摘要： Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to an existing qualified stacked silicon interconnect (SSI) technology programmable IC die (e.g., a super logic region (SLR)) without changing the programmable IC die (e.g., adding or removing blocks). One example integrated circuit (IC) package (200) generally includes a package substrate (202); at least one interposer (204) disposed above the package substrate (202) and comprising a plurality of interconnection lines (310, 312); a programmable IC die (302) disposed above the interposer (204); a fixed feature die (304) disposed above the interposer (204); and an interface die (306) disposed above the interposer (204) and configured to couple the programmable IC die (302) to the fixed feature die (304) using a first set of interconnection lines (310) routed through the interposer (204) between the programmable IC die (302) and the interface die (306) and a second set of interconnection lines (312) routed through the interposer (204) between the interface die (306) and the fixed feature die (304).
摘要翻译：描述了用于将一个或多个特征（例如，高带宽存储器（HBM））添加到现有的合格堆叠硅互连（SSI）技术可编程IC裸片（例如，超级逻辑区域（SLR）），而无需更改可编程IC芯片（例如添加或移除块）。一个示例集成电路（IC）封装200通常包括封装衬底202; 至少一个中介层（204），其设置在所述封装衬底（202）上方并且包括多条互连线（310,312）; 设置在所述中介层（204）上方的可编程IC管芯（302）; 布置在中介层（204）上方的固定特征模（304）; 以及布置在所述插入器（204）上方并且被配置为使用通过所述插入器（204）布线的第一组互连线（310）将所述可编程IC管芯（302）耦合到所述固定特征管芯（304）的接口管芯（306）在可编程IC管芯302与接口管芯306之间以及在接口管芯306与固定特征管芯304之间穿过中介层204的第二组互连线312之间。 p>

6. 发明申请

WO2013006211A1 METHOD AND APPARATUS FOR SELF-ANNEALING MULTI-DIE INTERCONNECT REDUNDANCY CONTROL 审中-公开
标题翻译：自适应多模连接冗余控制的方法与装置
公开(公告)号：WO2013006211A1
公开(公告)日：2013-01-10
申请号：PCT/US2012/024345
申请日：2012-02-08
申请人： XILINX, INC. , CAMAROTA, Rafael, C.
发明人： CAMAROTA, Rafael, C.
IPC分类号： H03K19/177 , H03K19/003 , H01L21/66
CPC分类号： H03K19/177 , H01L22/14 , H01L22/22 , H01L24/14 , H01L2224/14515 , H01L2224/16145 , H03K19/00392
摘要： An apparatus for interconnecting a first die (402) and a second die (404) of a multi-die device (400) includes a master circuit block (406) that interfaces with the first die of the multi-die device, a slave circuit block (408) that interfaces with the second die of the multi-die device, a first memory (416a-416e) in the slave circuit block, a second memory (430a-430e) in the master circuit block, and a plurality of μbumps (1 -6) between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the μbumps (3) as a faulty μbump, and store a first value that corresponds with the identified faulty μbump in the first memory.
摘要翻译：用于互连多芯片器件（400）的第一管芯（402）和第二管芯（404）的装置包括与多管芯器件的第一管芯连接的主电路块（406），从属电路与多管芯器件的第二管芯连接的块（408），从属电路块中的第一存储器（416a-416e），主电路块中的第二存储器（430a-430e）和多个μ片（1 -6），其中所述主电路块和从电路块被配置为将所述μbumps（3）中的一个识别为有缺陷的μbump，并且存储与所识别的对应的第一值第一个内存中存在错误的μbump。

7. 发明授权

EP2730028B1 METHOD AND APPARATUS FOR SELF-ANNEALING MULTI-DIE INTERCONNECT REDUNDANCY CONTROL 有权
公开(公告)号：EP2730028B1
公开(公告)日：2018-12-12
申请号：EP12706957.3
申请日：2012-02-08
申请人： Xilinx, Inc.
发明人： CAMAROTA, Rafael, C.
IPC分类号： H03K19/177 , H03K19/003 , H01L21/66
CPC分类号： H03K19/177 , H01L22/14 , H01L22/22 , H01L24/14 , H01L2224/14515 , H01L2224/16145 , H03K19/00392
摘要： An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of mubumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the mubumps as a faulty mubump, and store a first value that corresponds with the identified faulty mubump in the first memory.

8. 发明公开

EP2730028A1 METHOD AND APPARATUS FOR SELF-ANNEALING MULTI-DIE INTERCONNECT REDUNDANCY CONTROL 有权
标题翻译：用于控制冗余的方法和装置SELBSTAUSGLÜHENDEN更多芯片连接
公开(公告)号：EP2730028A1
公开(公告)日：2014-05-14
申请号：EP12706957.3
申请日：2012-02-08
申请人： Xilinx, Inc.
发明人： CAMAROTA, Rafael, C.
IPC分类号： H03K19/177 , H03K19/003 , H01L21/66
CPC分类号： H03K19/177 , H01L22/14 , H01L22/22 , H01L24/14 , H01L2224/14515 , H01L2224/16145 , H03K19/00392
摘要： An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of mubumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the mubumps as a faulty mubump, and store a first value that corresponds with the identified faulty mubump in the first memory.

9. 发明授权

EP3028304B1 DUAL PORT MEMORY CELL 有权
公开(公告)号：EP3028304B1
公开(公告)日：2020-05-06
申请号：EP14712151.1
申请日：2014-03-06
申请人： Xilinx, Inc.
发明人： CAMAROTA, Rafael, C.
IPC分类号： H01L27/11 , G11C8/16 , H01L29/78 , H01L27/088

10. 发明公开

EP3028304A1 DUAL PORT MEMORY CELL 有权
标题翻译：具有两个端口存储器单元
公开(公告)号：EP3028304A1
公开(公告)日：2016-06-08
申请号：EP14712151.1
申请日：2014-03-06
申请人： Xilinx, Inc.
发明人： CAMAROTA, Rafael, C.
IPC分类号： H01L27/11 , G11C8/16 , H01L29/78 , H01L27/088
摘要： A multi-port memory cell is disclosed that includes first and second cross-coupled inverter circuits. The input node of each inverter circuit is coupled to the output node of the other inverter circuit to receive the inverted output of the other inverter circuit. The multi-port memory cell includes a first pair of access transistors of a first type, each coupled to the input node of a respective one of the first and second inverter circuits. The multi-port memory cell also includes a second pair of access transistors of the second type, each coupled to the input of a respective one of the first and second inverter circuits. The multi-port cell exhibits advantages in layout compactness and SEU tolerance.

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