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    • 1. 发明授权
    • Output buffer circuit capable of enhancing stability
    • 输出缓冲电路,能够提高稳定性
    • US08803600B2
    • 2014-08-12
    • US13592368
    • 2012-08-23
    • Xie-Ren HsuJi-Ting ChenYao-Hung Kuo
    • Xie-Ren HsuJi-Ting ChenYao-Hung Kuo
    • H03F1/02
    • H03F1/56H03F1/34
    • An output buffer circuit capable of enhancing stability includes an operational amplifier, a capacitive load and an output control unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and generates an output voltage to the output terminal according to an input voltage received by the positive input terminal. The output control unit is coupled between the output terminal of the operational amplifier and the capacitive load, and is utilized for controlling electrical connection between the output terminal of the operational amplifier and the capacitive load to form a signal output path and for adjusting impedance of the signal output path when the signal output path is formed. The output control unit comprises a plurality of output switches for individually turning on or off the electrical connection between the output terminal and the capacitive load of the operational amplifier.
    • 能够提高稳定性的输出缓冲电路包括运算放大器,电容性负载和输出控制单元。 运算放大器具有正输入端子,负输入端子和输出端子,并且根据正输入端子接收的输入电压向输出端子产生输出电压。 输出控制单元耦合在运算放大器的输出端和电容性负载之间,用于控制运算放大器的输出端与电容性负载之间的电连接,形成信号输出路径,并用于调节 信号输出路径形成时的信号输出路径。 输出控制单元包括多个输出开关,用于单独地接通或关断运算放大器的输出端子和电容负载之间的电连接。
    • 2. 发明授权
    • Output buffer circuit capable of enhancing stability
    • 输出缓冲电路,能够提高稳定性
    • US08278999B2
    • 2012-10-02
    • US13014672
    • 2011-01-26
    • Xie-Ren HsuJi-Ting ChenYao-Hung Kuo
    • Xie-Ren HsuJi-Ting ChenYao-Hung Kuo
    • H03F1/02
    • H03F1/56H03F1/34
    • An output buffer circuit capable of enhancing stability includes an operational amplifier, a capacitive load and an output control unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and generates an output voltage to the output terminal according to an input voltage received by the positive input terminal. The output control unit is coupled between the output terminal of the operational amplifier and the capacitive load, and is utilized for controlling electrical connection between the output terminal of the operational amplifier and the capacitive load to form a signal output path and for adjusting impedance of the signal output path when the signal output path is formed.
    • 能够提高稳定性的输出缓冲电路包括运算放大器,电容性负载和输出控制单元。 运算放大器具有正输入端子,负输入端子和输出端子,并且根据正输入端子接收的输入电压向输出端子产生输出电压。 输出控制单元耦合在运算放大器的输出端和电容性负载之间,用于控制运算放大器的输出端与电容性负载之间的电连接,形成信号输出路径,并用于调节 信号输出路径形成时的信号输出路径。
    • 3. 发明申请
    • Output Buffer Circuit Capable of Enhancing Stability
    • 输出缓冲电路,提高稳定性
    • US20110187457A1
    • 2011-08-04
    • US13014672
    • 2011-01-26
    • Xie-Ren HsuJi-Ting ChenYao-Hung Kuo
    • Xie-Ren HsuJi-Ting ChenYao-Hung Kuo
    • H03F1/56
    • H03F1/56H03F1/34
    • An output buffer circuit capable of enhancing stability includes an operational amplifier, a capacitive load and an output control unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and generates an output voltage to the output terminal according to an input voltage received by the positive input terminal. The output control unit is coupled between the output terminal of the operational amplifier and the capacitive load, and is utilized for controlling electrical connection between the output terminal of the operational amplifier and the capacitive load to forma signal output path and for adjusting impedance of the signal output path when the signal output path is formed.
    • 能够提高稳定性的输出缓冲电路包括运算放大器,电容性负载和输出控制单元。 运算放大器具有正输入端子,负输入端子和输出端子,并且根据正输入端子接收的输入电压向输出端子产生输出电压。 输出控制单元耦合在运算放大器的输出端和容性负载之间,用于控制运算放大器的输出端与电容性负载之间的电连接,以形成信号输出路径,并用于调整信号的阻抗 当形成信号输出路径时的输出路径。
    • 4. 发明申请
    • Output Buffer Circuit Capable of Enhancing Stability
    • 输出缓冲电路,提高稳定性
    • US20120319770A1
    • 2012-12-20
    • US13592368
    • 2012-08-23
    • Xie-Ren HsuJi-Ting ChenYao-Hung Kuo
    • Xie-Ren HsuJi-Ting ChenYao-Hung Kuo
    • H03F1/34
    • H03F1/56H03F1/34
    • An output buffer circuit capable of enhancing stability includes an operational amplifier, a capacitive load and an output control unit. The operational amplifier has a positive input terminal, a negative input terminal and an output terminal, and generates an output voltage to the output terminal according to an input voltage received by the positive input terminal. The output control unit is coupled between the output terminal of the operational amplifier and the capacitive load, and is utilized for controlling electrical connection between the output terminal of the operational amplifier and the capacitive load to form a signal output path and for adjusting impedance of the signal output path when the signal output path is formed. The output control unit comprises a plurality of output switches for individually turning on or off the electrical connection between the output terminal and the capacitive load of the operational amplifier.
    • 能够提高稳定性的输出缓冲电路包括运算放大器,电容性负载和输出控制单元。 运算放大器具有正输入端子,负输入端子和输出端子,并且根据正输入端子接收的输入电压向输出端子产生输出电压。 输出控制单元耦合在运算放大器的输出端和电容性负载之间,用于控制运算放大器的输出端与电容性负载之间的电连接,形成信号输出路径,并用于调节 信号输出路径形成时的信号输出路径。 输出控制单元包括多个输出开关,用于单独地接通或关断运算放大器的输出端子和电容负载之间的电连接。
    • 5. 发明授权
    • Output buffer circuit and method for avoiding voltage overshoot
    • 输出缓冲电路及避免电压过冲的方法
    • US08487687B2
    • 2013-07-16
    • US12750671
    • 2010-03-30
    • Xie-Ren HsuJi-Ting Chen
    • Xie-Ren HsuJi-Ting Chen
    • H03K5/08H03F3/45
    • H03K19/018514G09G3/20G09G2310/0275G09G2310/0291H03F2200/441H03F2203/45136H03K5/08H03K5/2481H03K19/00361
    • An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.
    • 用于避免电压过冲的输出缓冲电路包括输入级,输出偏置电路,输出级,钳位电路和控制单元。 输入级包括用于接收输入电压的正输入端子和负输入端子。 输入级根据输入电压产生电流信号。 输出偏置电路耦合到输入级,用于根据电流信号产生动态偏置。 输出级耦合到输入级和输出偏置电路,包括反向耦合到正输入端的输出端和耦合到输出偏置电路和输出端的至少一个输出晶体管,用于提供驱动 根据动态偏置电流到输出端产生输出电压。
    • 6. 发明申请
    • Output Buffer Circuit and Method for Avoiding Voltage Overshoot
    • 输出缓冲电路及避免电压过冲的方法
    • US20110181336A1
    • 2011-07-28
    • US12750671
    • 2010-03-30
    • Xie-Ren HsuJi-Ting Chen
    • Xie-Ren HsuJi-Ting Chen
    • H03K5/08
    • H03K19/018514G09G3/20G09G2310/0275G09G2310/0291H03F2200/441H03F2203/45136H03K5/08H03K5/2481H03K19/00361
    • An output buffer circuit for avoiding voltage overshoot includes an input stage, an output bias circuit, an output stage, a clamp circuit, and a control unit. The input stage includes a positive input terminal, for receiving an input voltage, and a negative input terminal. The input stage generates a current signal according to the input voltage. The output bias circuit is coupled to the input stage, for generating a dynamic bias according to the current signal. The output stage is coupled to the input stage and the output bias circuit, including an output terminal, reversely coupled to the positive input terminal, and at least one output transistor, coupled to the output bias circuit and the output terminal, for providing a driving current to the output terminal according to the dynamic bias to generate an output voltage.
    • 用于避免电压过冲的输出缓冲电路包括输入级,输出偏置电路,输出级,钳位电路和控制单元。 输入级包括用于接收输入电压的正输入端子和负输入端子。 输入级根据输入电压产生电流信号。 输出偏置电路耦合到输入级,用于根据电流信号产生动态偏置。 输出级耦合到输入级和输出偏置电路,包括反向耦合到正输入端的输出端和耦合到输出偏置电路和输出端的至少一个输出晶体管,用于提供驱动 根据动态偏置电流到输出端产生输出电压。