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1. 发明授权

US08095707B2 Method for synchronization of peripherals with a central processing unit in an embedded system 有权
标题翻译：外设与嵌入式系统中的中央处理单元同步的方法
公开(公告)号：US08095707B2
公开(公告)日：2012-01-10
申请号：US12194060
申请日：2008-08-19
申请人： Xiaoqian Zhang , Zhiyong Guan , Qi Li
发明人： Xiaoqian Zhang , Zhiyong Guan , Qi Li
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F1/12
摘要： A method and apparatus for synchronizing I/O peripherals with a CPU in an embedded system is discussed. The method involves receiving an address from the CPU in response to a read and/or write access, translating the address received from the CPU to identify a I/O peripheral to be accessed, disabling the operation of the CPU and synchronizing a memory from the CPU clock domain to the clock domain of the identified I/O peripheral. Upon completion of the read/write access, the identified I/O peripheral sends an acknowledgment, the memory is then synchronized from the clock domain of the I/O peripheral to the CPU clock domain and the operation of the CPU is then enabled.In another embodiment, if the acknowledgement from the identified I/O peripheral is not received within a predefined time duration, reserved data is sent to the CPU and the operation/access can be restarted.
摘要翻译：讨论了嵌入式系统中的I / O外设与CPU同步的方法和装置。该方法包括响应于读和/或写访问从CPU接收地址，翻译从CPU接收的地址以识别要访问的I / O外设，禁止CPU的操作并使来自 CPU时钟域到所识别的I / O外设的时钟域。在完成读/写访问后，所识别的I / O外设发送确认，然后将存储器从I / O外设的时钟域同步到CPU时钟域，然后启用CPU的操作。在另一个实施例中，如果在预定义的持续时间内未接收到来自所识别的I / O外围设备的确认，则保留的数据被发送到CPU，并且可以重新启动操作/访问。

2. 发明授权

US08023594B1 Asynchronous biphase mark signal receivers and methods of operating same 有权
标题翻译：异步双相标记信号接收器和操作方法相同
公开(公告)号：US08023594B1
公开(公告)日：2011-09-20
申请号：US12171612
申请日：2008-07-11
申请人： Qi Li , Xiaoqian Zhang , Zhiyong Guan
发明人： Qi Li , Xiaoqian Zhang , Zhiyong Guan
IPC分类号： G03B41/00
CPC分类号： G11B20/1419 , G11B20/1403
摘要： A biphase mark signal receiver includes a data and clock recovery circuit. The data recovery circuit may include a coarse recovery stage and a fine recovery stage. The coarse recovery stage is configured to detect repeating occurrences of a first preamble (e.g., Y-preamble) within a biphase encoded data stream received by the data recovery circuit. The fine recovery stage is configured to generate a recovered data stream, in response to estimating a plurality of timing decision points (e.g., 3UI, 2UI and 1UI) from the repeating occurrences of the first preamble detected by the coarse recovery stage.
摘要翻译：双相标记信号接收机包括数据和时钟恢复电路。数据恢复电路可以包括粗略恢复阶段和精细恢复阶段。粗恢复级被配置为检测由数据恢复电路接收的双相编码数据流中的第一前同步码（例如，Y前同步码）的重复发生。精细恢复级被配置为响应于从粗恢复级检测到的第一前同步的重复出现来估计多个定时决定点（例如，3UI，2UI和1UI）来生成恢复的数据流。

3. 发明申请

US20100046557A1 MANAGING TRANSMIT JITTER FOR MULTI-FORMAT DIGITAL AUDIO TRANSMISSION 有权
标题翻译：管理用于多格式数字音频传输的发送器
公开(公告)号：US20100046557A1
公开(公告)日：2010-02-25
申请号：US12194080
申请日：2008-08-19
申请人： ZHIYONG GUAN , Xiaoqian Zhang , Qi Li
发明人： ZHIYONG GUAN , Xiaoqian Zhang , Qi Li
IPC分类号： H04L29/02
CPC分类号： H04N7/083 , G09G5/006 , G09G2370/12
摘要： A method of transmitting audio data across a digital interface is provided. The method includes receiving audio data, organized as a plurality of audio samples. At least one of the plurality of audio samples may be placed into a data packet. The data packet may be transmitted during a valid transmission interval if the data packet is full or during a valid transmission interval in response to receiving a packet send event.
摘要翻译：提供了一种通过数字接口传输音频数据的方法。该方法包括接收被组织为多个音频样本的音频数据。多个音频样本中的至少一个可以被放置在数据分组中。如果数据分组已满或响应于接收分组发送事件的有效传输间隔，则可以在有效传输间隔期间传输数据分组。

4. 发明授权

US08422518B2 Managing transmit jitter for multi-format digital audio transmission 有权
标题翻译：管理多格式数字音频传输的传输抖动
公开(公告)号：US08422518B2
公开(公告)日：2013-04-16
申请号：US12194080
申请日：2008-08-19
申请人： Zhiyong Guan , Xiaoqian Zhang , Qi Li
发明人： Zhiyong Guan , Xiaoqian Zhang , Qi Li
IPC分类号： H04J3/06
CPC分类号： H04N7/083 , G09G5/006 , G09G2370/12
摘要： A method of transmitting audio data across a digital interface is provided. The method includes receiving audio data, organized as a plurality of audio samples. At least one of the plurality of audio samples may be placed into a data packet. The data packet may be transmitted during a valid transmission interval if the data packet is full or during a valid transmission interval in response to receiving a packet send event.
摘要翻译：提供了一种通过数字接口传输音频数据的方法。该方法包括接收被组织为多个音频样本的音频数据。多个音频样本中的至少一个可以被放置在数据分组中。如果数据分组已满或响应于接收分组发送事件的有效传输间隔，则可以在有效传输间隔期间传输数据分组。

5. 发明授权

US08861669B2 Stream clock recovery in high definition multimedia digital system 有权
标题翻译：高清多媒体数字系统中的流时钟恢复
公开(公告)号：US08861669B2
公开(公告)日：2014-10-14
申请号：US12571210
申请日：2009-09-30
申请人： Xiaoqian Zhang , Shubing Zhai , Yanbo Wang
发明人： Xiaoqian Zhang , Shubing Zhai , Yanbo Wang
IPC分类号： H03D3/24 , H03L7/197 , H04N21/43 , H03L7/193 , H04N21/41 , H04J3/06 , G09G5/00
CPC分类号： H04J3/062 , G09G5/008 , H03L7/193 , H03L7/1978 , H04N21/4122 , H04N21/4307
摘要： The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.
摘要翻译：本公开提供了用于在高清晰度多媒体数字内容传输系统中的信宿处恢复源流时钟数据的技术。本公开包括基于分数N锁相环（PLL）的时钟发生器，可编程Σ-Δ调制器（SDM）和时钟数据校准器，以完全恢复原始源流时钟数据。分数N PLL提供灵活的源流时钟恢复。当原始时钟与再生时钟之间存在频率偏差时，时钟数据校准器控制电路调整时钟数据，防止任何流数据缓冲区溢出或下溢问题。所公开的技术基于DisplayPort和HDMI的标准与宿设备兼容。

6. 发明授权

US07750696B2 Phase-locked loop 有权
标题翻译：锁相环
公开(公告)号：US07750696B2
公开(公告)日：2010-07-06
申请号：US12077929
申请日：2008-03-20
申请人： Yanbo Wang , Xiaoqian Zhang , Shubing Zhai
发明人： Yanbo Wang , Xiaoqian Zhang , Shubing Zhai
IPC分类号： H03L7/06
CPC分类号： H03L7/18 , H03L7/0891
摘要： A method of calibrating a PLL that includes forcing a control voltage input to a voltage controlled oscillator to be a reference voltage and setting a calibration divider coupled to receive an output clock signal from the voltage controlled oscillator such that the calibration divider utilizes one of a plurality of divisors that results in the output clock signal having a high frequency can substantially avoid overshoot and glitch problems associated with conventional PLL calibrations.
摘要翻译：一种校准PLL的方法，其包括强制输入到压控振荡器的控制电压作为参考电压，并且设置耦合以从压控振荡器接收输出时钟信号的校准分配器，使得校准分配器利用多个导致输出时钟信号具有高频率的除数可以基本上避免与常规PLL校准相关的过冲和毛刺问题。

7. 发明授权

US08217689B2 Method and circuit for DisplayPort video clock recovery 有权
标题翻译： DisplayPort视频时钟恢复方法和电路
公开(公告)号：US08217689B2
公开(公告)日：2012-07-10
申请号：US12675106
申请日：2010-01-19
申请人： Lu Yang , Sibing Wang , Xiaoqian Zhang
发明人： Lu Yang , Sibing Wang , Xiaoqian Zhang
IPC分类号： H03L7/06
CPC分类号： H03L7/0807 , H03L7/16
摘要： A method and a circuit are described for recovery of video clocks for a DisplayPort receiver. The disclosure includes two clock dividers, a direct digital synthesis (DDS), a fixed multiplier Phase-Locked Loop (PLL) on a DisplayPort video system. A DisplayPort receiver link clock is divided to a lower frequency as the input of the DDS which can lower the performance requirement on a DDS circuit. The output from a time stamp value indirectly controls a direct digital synthesis device, which then drives a PLL to generate the recovery clock signal. The technique is suitable for implementation on an integrated circuit and Field Programmable Gate array system.
摘要翻译：描述了一种用于恢复DisplayPort接收机的视频时钟的方法和电路。本公开包括两个时钟分频器，直接数字合成（DDS），DisplayPort视频系统上的固定乘法器锁相环（PLL）。 DisplayPort接收器链路时钟被划分为较低频率作为DDS的输入，这可以降低DDS电路的性能要求。来自时间戳值的输出间接地控制直接数字合成装置，然后驱动PLL以产生恢复时钟信号。该技术适用于集成电路和现场可编程门阵列系统的实现。

8. 发明授权

US07571337B1 Integrated circuits and methods with transmit-side data bus deskew 有权
标题翻译：具有发射端数据总线偏移的集成电路和方法
公开(公告)号：US07571337B1
公开(公告)日：2009-08-04
申请号：US11136056
申请日：2005-05-24
申请人： Shubing Zhai , Xiaoqian Zhang
发明人： Shubing Zhai , Xiaoqian Zhang
IPC分类号： G06F13/42
CPC分类号： H04L7/0338 , G11C27/02 , H04L7/0008
摘要： A data output circuit includes a plurality of clocked data output buffers, each of which drives a data output thereof responsive to a clock signal and an adjustable multiphase clock signal generator that generates a plurality of clock signals of different phases and that is operative to shift the plurality of clock signals relative to a reference clock signal responsive to a first control signal. The data output circuit further includes a clock signal selector that selectively applies the plurality of clock signals to the data output buffers responsive to a second control signal. The adjustable multiphase clock signal generator may include, for example, a control loop, such as a phase locked loop or a delay locked loop, which selectively feeds back one of the plurality of clock signals responsive to the first control signal. The clock signal selector may include a plurality of clock signal selectors, respective ones of which receive the plurality of clock signals and selectively apply the plurality of clock signals to respective ones of the data output buffers responsive to the second control signal.
摘要翻译：数据输出电路包括多个时钟数据输出缓冲器，每个时钟数据输出缓冲器响应于时钟信号驱动其数据输出，以及可调多相时钟信号发生器，其产生不同相位的多个时钟信号，响应于第一控制信号的相对于参考时钟信号的多个时钟信号。数据输出电路还包括时钟信号选择器，其响应于第二控制信号而选择性地将多个时钟信号施加到数据输出缓冲器。可调节多相时钟信号发生器可以包括例如响应于第一控制信号选择性地反馈多个时钟信号中的一个的控制环路，例如锁相环或延迟锁定环路。时钟信号选择器可以包括多个时钟信号选择器，其中各个时钟信号选择器接收多个时钟信号，并且响应于第二控制信号有选择地将多个时钟信号施加到数据输出缓冲器中的相应数据输出缓冲器。

9. 发明申请

US20050226243A1 Method and apparatus for forwarding bursty data 有权
标题翻译：用于转发突发数据的方法和装置
公开(公告)号：US20050226243A1
公开(公告)日：2005-10-13
申请号：US10861897
申请日：2004-06-04
申请人： Shubing Zhai , Yefei Sun , Xiaoqian Zhang , Zhonghai Gan
发明人： Shubing Zhai , Yefei Sun , Xiaoqian Zhang , Zhonghai Gan
IPC分类号： H04L12/56 , H04L29/06 , H04L29/08
CPC分类号： H04L29/06 , H04L47/10 , H04L47/22 , H04L47/30 , H04L49/103 , H04L69/324
摘要： Data received from a bursty interface is received on a burst-by-burst basis. Once a burst is received, it is stored in a processing queue. A complete burst is received so long a processing queue can accommodate a data burst. The complete data burst is directed to an output and used to create a complete data burst on said output. The output burst is dispatched so long as a receiving port is able to accept the output burst.
摘要翻译：从突发接口接收的数据以突发为基础接收。一旦接收到脉冲串，它就被存储在处理队列中。接收到完整的脉冲串，处理队列可以容纳数据脉冲串。完整的数据脉冲串被引导到输出端，用于在所述输出端创建完整的数据脉冲串。只要接收端口能够接收输出脉冲串，就调度输出脉冲串。

10. 发明申请

US20110075782A1 STREAM CLOCK RECOVERY IN HIGH DEFINITION MULTIMEDIA DIGITAL SYSTEM 有权
标题翻译：高定义多媒体数字系统中的时钟恢复
公开(公告)号：US20110075782A1
公开(公告)日：2011-03-31
申请号：US12571210
申请日：2009-09-30
申请人： Xiaoqian Zhang , Shubing Zhai , Yanbo Wang
发明人： Xiaoqian Zhang , Shubing Zhai , Yanbo Wang
IPC分类号： H04L7/00
CPC分类号： H04J3/062 , G09G5/008 , H03L7/193 , H03L7/1978 , H04N21/4122 , H04N21/4307
摘要： The present disclosure provides techniques for recovering source stream clock data at the sink in a high definition multimedia digital content transport system. The disclosure includes a fractional-N Phase-Locked Loop (PLL) based clock generator, a programmable Sigma-Delta Modulator (SDM), and a clock data calibrator to fully recover the original source stream clock data. The fractional-N PLL provides flexible source stream clock recovery. When there is a frequency deviation between the original clock and the regenerated clock, the clock data calibrator control circuit adjusts the clock data, preventing any stream data buffer overflow or underflow problems. The disclosed techniques are compatible with the sink devices based on the standards of DisplayPort and HDMI.
摘要翻译：本公开提供了用于在高清晰度多媒体数字内容传输系统中的信宿处恢复源流时钟数据的技术。本公开包括基于分数N锁相环（PLL）的时钟发生器，可编程Σ-Δ调制器（SDM）和时钟数据校准器，以完全恢复原始源流时钟数据。分数N PLL提供灵活的源流时钟恢复。当原始时钟与再生时钟之间存在频率偏差时，时钟数据校准器控制电路调整时钟数据，防止任何流数据缓冲区溢出或下溢问题。所公开的技术基于DisplayPort和HDMI的标准与宿设备兼容。

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