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1. 发明授权

US09401330B1 IC package with non-uniform dielectric layer thickness 有权
标题翻译： IC封装具有不均匀的介电层厚度
公开(公告)号：US09401330B1
公开(公告)日：2016-07-26
申请号：US12578426
申请日：2009-10-13
申请人： Xiaohong Jiang , Hong Shi , Hui Liu , Yuanlin Xie
发明人： Xiaohong Jiang , Hong Shi , Hui Liu , Yuanlin Xie
IPC分类号： H01L23/538 , H01L23/12
CPC分类号： H01L23/5383 , H01L23/12 , H01L23/49822 , H01L23/50 , H01L23/64 , H01L24/13 , H01L24/16 , H01L24/32 , H01L24/73 , H01L24/92 , H01L2224/131 , H01L2224/16227 , H01L2224/32225 , H01L2224/73204 , H01L2224/73253 , H01L2224/92125 , H01L2924/14 , H01L2924/15311 , H01L2924/16195 , H01L2924/19041 , H01L2924/19105 , H01L2924/3011 , H01L2924/00 , H01L2924/014
摘要： An integrated circuit (IC) package substrate with non-uniform dielectric layers is disclosed. The IC package substrate is a multilayer package substrate that has dielectric layers and metal layers stacked up alternately. The dielectric layers in the package substrate have different thickness. The metal layers may be ground, signal or power layers. A thicker dielectric layer is placed in between a signal layer and a power layer in the package substrate. The thicker dielectric layer may be at least twice as thick as other dielectric layers in the package substrate. The thicker dielectric layer may provide better impedance control in the package substrate.
摘要翻译：公开了具有不均匀电介质层的集成电路（IC）封装基板。 IC封装基板是具有交替堆叠的电介质层和金属层的多层封装基板。封装衬底中的电介质层具有不同的厚度。金属层可以是接地，信号或功率层。在封装衬底中的信号层和功率层之间放置较厚的介电层。较厚的电介质层可以是封装衬底中其它电介质层的至少两倍。较厚的介电层可以在封装衬底中提供更好的阻抗控制。

2. 发明授权

US08841561B1 High performance PCB 有权
标题翻译：高性能PCB
公开(公告)号：US08841561B1
公开(公告)日：2014-09-23
申请号：US12714156
申请日：2010-02-26
申请人： Xiaohong Jiang , Hong Shi
发明人： Xiaohong Jiang , Hong Shi
IPC分类号： H05K1/11 , H05K1/02
CPC分类号： H05K1/0219 , H05K1/0222 , H05K1/0225 , H05K1/025 , H05K1/0253 , H05K1/111 , H05K1/113 , H05K2201/09227 , H05K2201/09618
摘要： In one embodiment, a printed circuit board (PCB) comprises one or more signal contact pads on a surface of the PCB and a plurality of ground planes embedded in the PCB with at least the ground plane closest to the signal contact pads) having gaps in line with the trace(s). In another embodiment, a PCB comprises one or more signal traces on a first surface of the PCB, a plurality of ground planes embedded in the PCB, and at least one blind via interconnecting the ground planes. In still another embodiment, a PCB comprises one or more signal contact pads on a first surface of the PCB, a plurality of ground planes embedded in the PCB with at least the ground plane closest to the signal contact pad(s) having a gap in line with the signal contact pad(s), and at least one blind via interconnecting the ground planes. In still another embodiment, signal contact pads may be formed on both major surfaces of the PCB.
摘要翻译：在一个实施例中，印刷电路板（PCB）包括在PCB的表面上的一个或多个信号接触焊盘和嵌入到PCB中的至少接地平面的多个接地平面，其具有最接近信号接触焊盘的接地平面）与痕迹一致。在另一个实施例中，PCB包括在PCB的第一表面上的一个或多个信号迹线，嵌入PCB中的多个接地平面以及互连地平面的至少一个盲通孔。在另一个实施例中，PCB包括在PCB的第一表面上的一个或多个信号接触焊盘，嵌入在PCB中的至少接地平面的多个接地平面与至少具有间隙的信号接触焊盘与信号接触焊盘线连接，以及至少一个盲孔通过互连地平面。在另一个实施例中，信号接触焊盘可以形成在PCB的两个主表面上。

3. 发明申请

US20100148375A1 Vertically Tapered Transmission Line for Optimal Signal Transition in High-Speed Multi-Layer Ball Grid Array Packages 有权
标题翻译：垂直锥形传输线，用于高速多层球栅阵列封装中的最佳信号转换
公开(公告)号：US20100148375A1
公开(公告)日：2010-06-17
申请号：US12713842
申请日：2010-02-26
申请人： Xiaohong Jiang , Hong Shi
发明人： Xiaohong Jiang , Hong Shi
IPC分类号： H01L23/522 , H05K1/18
CPC分类号： G06F17/5072 , G06F2217/40 , H01L21/4857 , H01L23/49816 , H01L23/49822 , H01L2224/16225 , H01L2924/15311 , H05K1/0251 , H05K3/0005 , H05K3/4602 , H05K2201/09627 , H05K2201/09709
摘要： Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges.
摘要翻译：概括而言，本发明的实施例满足了对多层BGA封装中的最佳信号转换设计垂直传输线的方法的需求。通过控制封装中每个微通孔中的微通孔的阻抗和几何连续性，以跟随层间的平滑阻抗和几何曲线，可以将传输线的回波损耗和插入损耗减小或控制在可接受的范围内。

4. 发明申请

US20090077523A1 VERTICALLY TAPERED TRANSMISSION LINE FOR OPTIMAL SIGNAL TRANSITION IN HIGH-SPEED MULTI-LAYER BALL GRID ARRAY PACKAGES 失效
标题翻译：用于高速多层球网阵列中的最佳信号转换的垂直传输线
公开(公告)号：US20090077523A1
公开(公告)日：2009-03-19
申请号：US11857940
申请日：2007-09-19
申请人： Xiaohong Jiang , Hong Shi
发明人： Xiaohong Jiang , Hong Shi
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/40 , H01L21/4857 , H01L23/49816 , H01L23/49822 , H01L2224/16225 , H01L2924/15311 , H05K1/0251 , H05K3/0005 , H05K3/4602 , H05K2201/09627 , H05K2201/09709
摘要： Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges.
摘要翻译：概括而言，本发明的实施例满足了对多层BGA封装中的最佳信号转换设计垂直传输线的方法的需求。通过控制封装中每个微通孔中的微通孔的阻抗和几何连续性，以跟随层间的平滑阻抗和几何曲线，可以将传输线的回波损耗和插入损耗减小或控制在可接受的范围内。

5. 发明授权

US08502386B2 Vertically tapered transmission line for optimal signal transition in high-speed multi-layer ball grid array packages 有权
标题翻译：垂直锥形传输线，用于高速多层球栅阵列封装中的最佳信号转换
公开(公告)号：US08502386B2
公开(公告)日：2013-08-06
申请号：US12713842
申请日：2010-02-26
申请人： Xiaohong Jiang , Hong Shi
发明人： Xiaohong Jiang , Hong Shi
IPC分类号： H01L23/48
CPC分类号： G06F17/5072 , G06F2217/40 , H01L21/4857 , H01L23/49816 , H01L23/49822 , H01L2224/16225 , H01L2924/15311 , H05K1/0251 , H05K3/0005 , H05K3/4602 , H05K2201/09627 , H05K2201/09709
摘要： Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges.
摘要翻译：概括而言，本发明的实施例满足了对多层BGA封装中的最佳信号转换设计垂直传输线的方法的需求。通过控制封装中每个微通孔中的微通孔的阻抗和几何连续性，以跟随层间的平滑阻抗和几何曲线，可以将传输线的回波损耗和插入损耗减小或控制在可接受的范围内。

6. 发明授权

US08368174B1 Compensation network using an on-die compensation inductor 有权
标题翻译：补偿网络使用片上补偿电感
公开(公告)号：US08368174B1
公开(公告)日：2013-02-05
申请号：US12833888
申请日：2010-07-09
申请人： Xiaohong Jiang , Hong Shi
发明人： Xiaohong Jiang , Hong Shi
IPC分类号： H01L27/08
CPC分类号： H01L23/5227 , H01L23/645 , H01L2224/16225 , H01L2924/15311 , H05K1/0243
摘要： An integrated circuit with an on-die compensation network is presented. The compensation network includes a compensation inductor that has one terminal coupled to a bump pad of the die. Another terminal of the inductor is connected to a metal layer underneath the compensation inductor, forming a pi-configuration with the bump pad. The metal layer routes input and output signals from the integrated circuit. The invention can be used in either flip chip or wire bond applications.
摘要翻译：提出了一种具有片上补偿网络的集成电路。补偿网络包括补偿电感器，其具有耦合到管芯的凸块焊盘的一个端子。电感器的另一个端子连接到补偿电感器下面的金属层，形成具有凸块焊盘的pi构型。金属层从集成电路路由输入和输出信号。本发明可以用于倒装芯片或引线键合应用。

7. 发明授权

US08294259B2 Interconnect pattern for transceiver package 有权
标题翻译：收发器封装的互连模式
公开(公告)号：US08294259B2
公开(公告)日：2012-10-23
申请号：US12702789
申请日：2010-02-09
申请人： Xiaohong Jiang , Hong Shi
发明人： Xiaohong Jiang , Hong Shi
IPC分类号： H01L23/48
CPC分类号： H01L23/66 , H01L23/50 , H01L23/5286 , H01L2223/6638 , H01L2924/0002 , H01L2924/19051 , H01L2924/3011 , H01L2924/00
摘要： In one embodiment, signaling and ground contacts are located in at least two parallel, rectilinear rows along at least one edge of an interconnect package such as a BGA package. In one row, each of a plurality of ground contacts is located between two pairs of contacts for receiving differential signals. In the second row, each of a plurality of ground contacts is located between two pairs of contacts for transmitting differential signals and the ground contacts in the second row are offset by one column from the ground contacts in the first row. As a result, the ratio of signaling pairs to ground contacts is 2:2. Additional pairs of rows may also be used. In other embodiments, signaling and ground contacts are located in three parallel, rectilinear rows along at least one edge of the package.
摘要翻译：在一个实施例中，信号和接地触点沿着诸如BGA封装的互连封装的至少一个边缘位于至少两个平行的直线行中。在一行中，多个接地触点中的每一个位于两对触点之间，用于接收差分信号。在第二行中，多个接地触点中的每一个位于用于传输差分信号的两对触点之间，并且第二行中的接地触点与第一行中的接地触点偏移一列。因此，信号对与接地触点的比例为2：2。还可以使用附加的行对。在其他实施例中，信号和接地触点沿着封装的至少一个边缘位于三条平行的直线行中。

8. 发明申请

US20110193233A1 INTERCONNECT PATTERN FOR TRANSCEIVER PACKAGE 有权
公开(公告)号：US20110193233A1
公开(公告)日：2011-08-11
申请号：US12702789
申请日：2010-02-09
申请人： Xiaohong Jiang , Hong Shi
发明人： Xiaohong Jiang , Hong Shi
IPC分类号： H01L23/48
CPC分类号： H01L23/66 , H01L23/50 , H01L23/5286 , H01L2223/6638 , H01L2924/0002 , H01L2924/19051 , H01L2924/3011 , H01L2924/00
摘要： In one embodiment, signaling and ground contacts are located in at least two parallel, rectilinear rows along at least one edge of an interconnect package such as a BGA package. In one row, each of a plurality of ground contacts is located between two pairs of contacts for receiving differential signals. In the second row, each of a plurality of ground contacts is located between two pairs of contacts for transmitting differential signals and the ground contacts in the second row are offset by one column from the ground contacts in the first row. As a result, the ratio of signaling pairs to ground contacts is 2:2. Additional pairs of rows may also be used. In other embodiments, signaling and ground contacts are located in three parallel, rectilinear rows along at least one edge of the package. In the first row, ground contacts alternate with contacts for receiving differential signals and in the second row ground contacts alternate with contacts for transmitting differential signals. The third row of contacts is located between the first and second rows and contains contacts for receiving differential signals that alternate with contacts for transmitting differential signals. The ground contacts in the second row are offset by one column from the ground contacts in the first row. In a second embodiment, the receiving contacts in the third row are in the same column as the receiving contacts in the first row; and the transmitting contacts in the third row are in the same column as the transmitting contacts in the second row. In a third embodiment, the contacts in the third row are offset by one column from the corresponding contacts in the first or second rows. Each pair of contacts for receiving differential signals is formed by a contact in the first row and an adjacent contact in the third row; and each pair of contacts for transmitting differential signals is formed by a contact in the second row and an adjacent contact in the third row.

9. 发明授权

US07752587B2 Vertically tapered transmission line for optimal signal transition in high-speed multi-layer ball grid array packages 失效
标题翻译：垂直锥形传输线，用于高速多层球栅阵列封装中的最佳信号转换
公开(公告)号：US07752587B2
公开(公告)日：2010-07-06
申请号：US11857940
申请日：2007-09-19
申请人： Xiaohong Jiang , Hong Shi
发明人： Xiaohong Jiang , Hong Shi
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G06F2217/40 , H01L21/4857 , H01L23/49816 , H01L23/49822 , H01L2224/16225 , H01L2924/15311 , H05K1/0251 , H05K3/0005 , H05K3/4602 , H05K2201/09627 , H05K2201/09709
摘要： Broadly speaking, the embodiments of the present invention fill the need for methods of designing vertical transmission lines for optimal signal transition in multi-layer BGA packages. By controlling the impedance and geometry continuity of micro vias in each micro via layer in the package to follow smooth impedance and geometry curves from layer to layer, the return loss and insertion loss of the transmission line can be reduced or controlled to within acceptable ranges.
摘要翻译：概括而言，本发明的实施例满足了对多层BGA封装中的最佳信号转换设计垂直传输线的方法的需求。通过控制封装中每个微通孔中的微通孔的阻抗和几何连续性，以跟随层间的平滑阻抗和几何曲线，可以将传输线的回波损耗和插入损耗减小或控制在可接受的范围内。

10. 发明授权

US06972236B2 Semiconductor device layout and channeling implant process 有权
标题翻译：半导体器件布局和沟道植入过程
公开(公告)号：US06972236B2
公开(公告)日：2005-12-06
申请号：US10768612
申请日：2004-01-30
申请人： Yisuo Li , Xiaohong Jiang , Francis Benistant
发明人： Yisuo Li , Xiaohong Jiang , Francis Benistant
IPC分类号： H01L21/265 , H01L21/336 , H01L29/04 , H01L29/76 , H01L29/772
CPC分类号： H01L29/66659 , H01L21/26586 , H01L29/045
摘要： A device structure and method for forming graded junction using a implant process. Embodiments of the invention comprise implanting ions into said silicon substrate to form doped regions adjacent to said gate. The orientation of the channel region in the Si crystal structure (channel direction ) in combination with the large angle tilt and twist implant process produce doped regions that have a more graded junction. The orientation and implant process creates more channeling of ions. The channeling of ions creates a more graded junction. When implemented on a HV MOS TX, the graded junction of the LDD increases the breakdown voltage. Another embodiment is a FET with an annular shaped channel region.
摘要翻译：一种使用植入过程形成分级结的装置结构和方法。本发明的实施例包括将离子注入到所述硅衬底中以形成与所述栅极相邻的掺杂区域。 Si晶体结构中的沟道区域（沟道方向<100>）与大角度倾斜和扭曲注入工艺相结合的方向产生具有更梯度结的掺杂区域。取向和植入过程产生更多的离子通道。离子的通道产生更分级的结。当在HV MOS TX上实现时，LDD的分级结增加了击穿电压。另一实施例是具有环形通道区域的FET。

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