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1. 发明授权

US07188324B1 Assertion morphing in functional verification of integrated circuit design 有权
标题翻译：集成电路设计功能验证中的断言变形
公开(公告)号：US07188324B1
公开(公告)日：2007-03-06
申请号：US10893472
申请日：2004-07-16
申请人： Xiaogang Qiu , Si-En Chang
发明人： Xiaogang Qiu , Si-En Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G01R31/318364
摘要： A method and apparatus provides a mechanism to transform or “morph” Formal verification method assertions so that an assertion defined in one Design Under Test (DUT) can be replicated, or derived, to propagate into other related DUTs. Using the method and apparatus of the present invention, individual DUTs can better leverage assertions defined independently in other DUT environments. This, in turn, provides for greater productivity and a faster, smoother verification process-using Formal and Assertion Based Verification methods.
摘要翻译：一种方法和装置提供了一种转换或“变形”形式验证方法断言的机制，使得可以复制或导出在一个被测设计（DUT）中定义的断言传播到其他相关的DUT。使用本发明的方法和装置，各个DUT可以更好地利用在其它DUT环境中独立定义的断言。反过来，使用正式和断言验证方法，提供更高的生产力和更快，更平滑的验证过程。

2. 发明授权

US07509643B2 Method and apparatus for supporting asymmetric multi-threading in a computer system 有权
标题翻译：在计算机系统中支持不对称多线程的方法和装置
公开(公告)号：US07509643B2
公开(公告)日：2009-03-24
申请号：US10396891
申请日：2003-03-24
申请人： Xiaogang Qiu , Si-En Chang
发明人： Xiaogang Qiu , Si-En Chang
IPC分类号： G06F9/46
CPC分类号： G06F9/4881 , G06F9/3851 , G06F9/3885 , G06F9/50
摘要： One embodiment of the present invention facilitates favoring the performance of a single-threaded application in a computer system that supports simultaneous multi-threading (SMT), wherein multiple threads of execution simultaneously execute in an interleaved manner on functional units within a processor. During operation, the system maintains a priority for each simultaneously executing thread. The system uses these priorities in allocating a shared computational resource between the simultaneously executing threads, so that a thread with a higher priority is given preferential access to the shared computational resource. This asymmetric treatment of the threads enables+ the system to favor the performance of a single-threaded application while performing simultaneous multi-threading.
摘要翻译：本发明的一个实施例有助于支持同时多线程（SMT）的计算机系统中的单线程应用的性能，其中多个执行线程以交错的方式在处理器内的功能单元上执行。在运行期间，系统保持每个同时执行的线程的优先级。系统使用这些优先级在同时执行的线程之间分配共享计算资源，使得具有较高优先级的线程被给予对共享计算资源的优先访问。线程的这种不对称处理使得+系统在执行同时多线程时有利于单线程应用程序的性能。

3. 发明授权

US07444549B1 Method and apparatus for facilitating debugging of an integrated circuit 有权
标题翻译：用于促进集成电路调试的方法和装置
公开(公告)号：US07444549B1
公开(公告)日：2008-10-28
申请号：US11033616
申请日：2005-01-11
申请人： Si-En Chang
发明人： Si-En Chang
IPC分类号： G06F11/00
CPC分类号： G06F11/348 , G06F11/3409 , G06F11/3466 , G06F2201/86 , G06F2201/87 , G06F2201/88 , G06F2201/885
摘要： One embodiment of the present invention provides a system that facilitates debugging an integrated circuit without probing signal lines within the integrated circuit. During operation the system updates a performance counter within the integrated circuit based on the occurrence of one or more performance events. Note that some integrated circuits already include a performance counter which is used to measure the performance of the integrated circuit. Next, the system triggers a debugging operation based on the content of the performance counter, thereby facilitating debugging of the integrated circuit without probing signal lines within the integrated circuit. By using the performance counter to trigger the debugging operation in addition to measuring performance, the present invention can substantially reduce the amount of additional circuitry required to facilitate debugging of the integrated circuit.
摘要翻译：本发明的一个实施例提供一种便于调试集成电路而不在集成电路内探测信号线的系统。在操作期间，系统基于一个或多个性能事件的发生来更新集成电路内的性能计数器。请注意，一些集成电路已经包括用于测量集成电路性能的性能计数器。接下来，系统基于性能计数器的内容触发调试操作，从而有助于集成电路的调试，而不会在集成电路内探测信号线。除了测量性能之外，通过使用性能计数器来触发调试操作，本发明可以显着地减少便于调试集成电路所需的附加电路的数量。

4. 发明申请

US20090164877A1 MEMO VOICE RECORDING/PLAYBACK METHOD AND DIGITAL PHOTO FRAME USING THE SAME 审中-公开
标题翻译：备忘录音/回放方法和使用相同的数码相框
公开(公告)号：US20090164877A1
公开(公告)日：2009-06-25
申请号：US12272725
申请日：2008-11-17
申请人： Si-En Chang , Kun-Shien Tsai , Ching-Hung Wu , Ming-Deng Hsieh , Ming-Tsai Hsu
发明人： Si-En Chang , Kun-Shien Tsai , Ching-Hung Wu , Ming-Deng Hsieh , Ming-Tsai Hsu
IPC分类号： G06F17/00 , G10L21/00
CPC分类号： H04N5/775 , G11B27/034 , G11B27/11 , G11C2207/16 , H04N21/42203 , H04N21/4325 , H04N21/4334 , H04N21/8106 , H04N21/8153
摘要： A memo voice recording/playback method and a digital photo frame using the method are provided. The method is suitable for a digital image playback apparatus. The digital image playback apparatus has memo voice recording function and memo voice playback function and includes a display unit for image displaying. The method includes: displaying an image; judging whether memo voice recording function of the digital image playback apparatus is enabled or not; and executing a memo voice recording procedure to edit the recorded memo voice into a memo voice file associated with the image if it is judged that the memo voice recording function is enabled.
摘要翻译：提供了使用该方法的备忘录录音/播放方法和数码相框。该方法适用于数字图像播放装置。数字图像播放装置具有备注语音记录功能和备忘录语音播放功能，并且包括用于图像显示的显示单元。该方法包括：显示图像; 判断数字图像播放装置的备忘录录音功能是否启用; 以及如果判断为所述备忘录录音功能被使能，则执行备忘录录音过程以将所记录的备忘录语音编辑成与所述图像相关联的备忘录语音文件。

5. 发明授权

US06728938B2 Knowledge-based intelligent full scan dump processing methodology 有权
标题翻译：基于知识的智能全扫描转储处理方法
公开(公告)号：US06728938B2
公开(公告)日：2004-04-27
申请号：US10132916
申请日：2002-04-26
申请人： Si-En Chang
发明人： Si-En Chang
IPC分类号： G06F1750
CPC分类号： G06F11/267 , G01R31/318544 , G01R31/318569
摘要： A systematic methodology to analyze a full scan dump is presented. The methodology is knowledge-based, i.e., the methodology intelligently processes a full scan dump using knowledge of the system from which the full scan is obtained.
摘要翻译：介绍了分析全扫描转储的系统方法。该方法是基于知识的，即该方法使用从其获得全扫描的系统的知识来智能地处理全扫描转储。

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