专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100111047A1 Techniques to support multiple radio-access technologies 有权
标题翻译：支持多种无线电接入技术的技术
公开(公告)号：US20100111047A1
公开(公告)日：2010-05-06
申请号：US12384502
申请日：2009-04-06
申请人： Xiangying Yang , Muthu Venkatachalam , Pouya Taaghol , Shantidev Mohanty
发明人： Xiangying Yang , Muthu Venkatachalam , Pouya Taaghol , Shantidev Mohanty
IPC分类号： H04J3/00
CPC分类号： H04W72/1215 , H04W52/0216 , H04W52/028 , H04W88/10 , Y02D70/1224 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/146 , Y02D70/162 , Y02D70/164 , Y02D70/24
摘要： Techniques to permit scheduling of mixed radio access technologies. In some cases, a first radio access technology mode of a base station is scheduled during a first time region and a second radio access technology mode of a base station is scheduled during a sleep mode of the first radio access technology mode. In some cases, a first radio access technology mode of a base station is scheduled during a first time region and a second radio access technology mode of a base station is scheduled during an unused portion of the first time region. In some cases, a femto-base station is scheduled to snoop for local mobile stations during a sleep mode. Inactive regions of mobile stations are scheduled during a portion of sleep modes of the radio access technology modes.
摘要翻译：允许调度混合无线电接入技术的技术。在一些情况下，在第一时间区域期间调度基站的第一无线电接入技术模式，并且在第一无线电接入技术模式的睡眠模式期间调度基站的第二无线电接入技术模式。在一些情况下，在第一时间区域期间调度基站的第一无线电接入技术模式，并且在第一时间区域的未使用部分期间调度基站的第二无线电接入技术模式。在某些情况下，毫微微基站被安排在睡眠模式期间窥探本地移动台。在无线电接入技术模式的睡眠模式的一部分期间调度移动台的非活动区域。

2. 发明授权

US07391776B2 Microengine to network processing engine interworking for network processors 有权
标题翻译：微型引擎网络处理引擎互联网络处理器
公开(公告)号：US07391776B2
公开(公告)日：2008-06-24
申请号：US10738407
申请日：2003-12-16
申请人： Muthu Venkatachalam , Daniel G. Borkowski
发明人： Muthu Venkatachalam , Daniel G. Borkowski
IPC分类号： H04L12/56
CPC分类号： H04L29/06 , H04L69/12 , H04L69/324
摘要： A method and apparatus to control interaction between two multi-threaded processor engines is presented. A first multi-threaded processor engine is configured for connection to a serial link, and performs receive and transmit operations in a first “PHY” mode of operation. A second multi-threaded processor engine is operable to process data received by the first multi-threaded processor over the serial link and to provide the processed data to the first multi-threaded processor engine for transmission over the serial link, when the first multi-threaded processor operates in the PHY mode. Additionally, the first multi-threaded processor engine is configured to execute certain operations, e.g., hardware accelerator operations, at the request of the second multi-threaded processor engine in a second “co-processor” mode of operation.
摘要翻译：提出了一种控制两个多线程处理器引擎之间交互的方法和装置。第一多线程处理器引擎被配置为连接到串行链路，并且以第一“PHY”操作模式执行接收和发送操作。第二多线程处理器引擎可操作以通过串行链路处理由第一多线程处理器接收的数据，并且当第一多线程处理器引擎在第一多线程处理器引擎上传送时，线程处理器在PHY模式下工作。另外，第一多线程处理器引擎被配置为以第二“协处理器”操作模式在第二多线程处理器引擎的请求下执行某些操作，例如硬件加速器操作。

3. 发明授权

US09270457B2 Optimizing security bits in a media access control (MAC) header 有权
标题翻译：优化媒体访问控制（MAC）头中的安全位
公开(公告)号：US09270457B2
公开(公告)日：2016-02-23
申请号：US12347872
申请日：2008-12-31
申请人： David Johnston , Muthu Venkatachalam
发明人： David Johnston , Muthu Venkatachalam
IPC分类号： H04K1/00 , H04L9/08 , H04W12/02 , H04L29/06
CPC分类号： H04L9/0891 , H04L69/22 , H04L2209/80 , H04W12/02
摘要： A method of retrieving security information in a media access control (MAC) header by a wireless station may include receiving a data unit, such as a protocol data unit (PDU), from a remote wireless station. The PDU may include the MAC header. The method may also include reading two encryption key sequence (EKS) bits in the MAC header that denote both whether the data unit is encrypted and a position in an encryption key sequence for the data unit.
摘要翻译：通过无线站检索媒体访问控制（MAC）报头中的安全信息的方法可以包括从远程无线站接收诸如协议数据单元（PDU）的数据单元。 PDU可以包括MAC报头。该方法还可以包括读取MAC报头中的两个加密密钥序列（EKS）位，其表示数据单元是否被加密，以及数据单元的加密密钥序列中的位置。

4. 发明申请

US20050149602A1 Microengine to network processing engine interworking for network processors 有权
标题翻译：微型引擎网络处理引擎互联网络处理器
公开(公告)号：US20050149602A1
公开(公告)日：2005-07-07
申请号：US10738407
申请日：2003-12-16
申请人： Muthu Venkatachalam , Daniel Borkowski
发明人： Muthu Venkatachalam , Daniel Borkowski
IPC分类号： G06F15/16 , H04L29/06 , H04L29/08
CPC分类号： H04L29/06 , H04L69/12 , H04L69/324
摘要： A method and apparatus to control interaction between two multi-threaded processor engines is presented. A first multi-threaded processor engine is configured for connection to a serial link, and performs receive and transmit operations in a first “PHY” mode of operation. A second multi-threaded processor engine is operable to process data received by the first multi-threaded processor over the serial link and to provide the processed data to the first multi-threaded processor engine for transmission over the serial link, when the first multi-threaded processor operates in the PHY mode. Additionally, the first multi-threaded processor engine is configured to execute certain operations, e.g., hardware accelerator operations, at the request of the second multi-threaded processor engine in a second “co-processor” mode of operation.
摘要翻译：提出了一种控制两个多线程处理器引擎之间交互的方法和装置。第一多线程处理器引擎被配置为连接到串行链路，并且以第一“PHY”操作模式执行接收和发送操作。第二多线程处理器引擎可操作以通过串行链路处理由第一多线程处理器接收的数据，并且当第一多线程处理器引擎在第一多线程处理器引擎上传送时，线程处理器在PHY模式下工作。另外，第一多线程处理器引擎被配置为以第二“协处理器”操作模式在第二多线程处理器引擎的请求下执行某些操作，例如硬件加速器操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式