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1. 发明申请

WO2020101834A1 CIRCUIT AND METHOD FOR ENSURING A STABLE IO INTERFACE DURING PARTIAL RECONFIGURATION OF A REPROGRAMMABLE INTEGRATED CIRCUIT DEVICE 审中-公开
公开(公告)号：WO2020101834A1
公开(公告)日：2020-05-22
申请号：PCT/US2019/056497
申请日：2019-10-16
申请人： XILINX, INC.
发明人： SCHULTZ, David P. , ROBINSON, David , BATHALA, Kusuma , SONG, Wenyi
IPC分类号： H03K19/17736 , H03K19/17752 , H03K19/17756 , H03K19/1776
摘要： A circuit (300) for routing data (Data) in an integrated circuit device is described. The circuit (300) comprises an input/output port (307); an interface circuit (301) coupled to the input/output port and configured to receive data (Data), the interface circuit comprising a selection circuit (310) enabling the selection of the data and a predetermined value (Constant 2); and a control circuit (311) coupled to control the selection circuit (310); wherein the control circuit holds the input/output port at the predetermined value (Constant 2) during a partial reconfiguration (hold) of the integrated circuit device in response to a control signal (311 out). A method of configuring a circuit for routing data in an integrated circuit device is also described (fig. 12).

2. 发明申请

WO2016076963A1 SYSTEM AND METHOD FOR PREPARING PARTIALLY RECONFIGURABLE CIRCUIT DESIGNS 审中-公开
标题翻译：用于准备部分可重构电路设计的系统和方法
公开(公告)号：WO2016076963A1
公开(公告)日：2016-05-19
申请号：PCT/US2015/053324
申请日：2015-09-30
申请人： XILINX, INC.
发明人： SHIRAZI, Nabeel , ROBINSON, David , KASAT, Amit , SUNDARARAJAN, Arvind
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/505
摘要： A circuit design is created (202) in a computer memory in response to user input to a computer processor. The circuit design has a static portion (102). A virtual socket (312) is instantiated (204) in the circuit design in response to user input, and one or more reconfigurable modules (402, 404, 406) are instantiated (206) in the virtual socket in response to user input. The static portion of the circuit design is coupled (210) to the one or more reconfigurable modules, and configuration data are generated (212) from the circuit design. The configuration data include a configuration bitstream corresponding to the static portion of the circuit design and one or more partial configuration bitstreams corresponding to the one or more reconfigurable modules.
摘要翻译：响应于用户对计算机处理器的输入，在计算机存储器中创建电路设计（202）。电路设计具有静态部分（102）。响应于用户输入，在电路设计中实例化虚拟插座（312）（204），并且响应于用户输入，虚拟插座中的一个或多个可重新配置模块（402,404,406）被实例化（206）。电路设计的静态部分耦合（210）到一个或多个可重新配置的模块，并且从电路设计生成（212）配置数据。配置数据包括对应于电路设计的静态部分的配置比特流和对应于一个或多个可重新配置模块的一个或多个部分配置比特流。

3. 发明申请

WO2021055602A1 TRACING STATUS OF A PROGRAMMABLE DEVICE 审中-公开
公开(公告)号：WO2021055602A1
公开(公告)日：2021-03-25
申请号：PCT/US2020/051268
申请日：2020-09-17
申请人： XILINX, INC.
发明人： SCHULTZ, David, P. , HERNANDEZ, Adrian, M. , ROBINSON, David , TAGGART, Elessar , HEIMER, Max
IPC分类号： G06F8/60 , G06F8/61
摘要： Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.

4. 发明公开

EP4031963A1 TRACING STATUS OF A PROGRAMMABLE DEVICE 有权
公开(公告)号：EP4031963A1
公开(公告)日：2022-07-27
申请号：EP20781703.2
申请日：2020-09-17
申请人： Xilinx, Inc.
发明人： SCHULTZ, David, P. , HERNANDEZ, Adrian, M. , ROBINSON, David , TAGGART, Elessar , HEIMER, Max
IPC分类号： G06F8/60 , G06F8/61

5. 发明公开

EP3850753A1 CIRCUIT AND METHOD FOR ENSURING A STABLE IO INTERFACE DURING PARTIAL RECONFIGURATION OF A REPROGRAMMABLE INTEGRATED CIRCUIT DEVICE 审中-实审
公开(公告)号：EP3850753A1
公开(公告)日：2021-07-21
申请号：EP19853274.9
申请日：2019-10-16
申请人： Xilinx, Inc.
发明人： SCHULTZ, David P. , ROBINSON, David , BATHALA, Kusuma , SONG, Wenyi
IPC分类号： H03K19/17736 , H03K19/17752 , H03K19/17756 , H03K19/1776

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