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1. 发明申请

WO2022098396A8 TEMPERATURE-LOCKED LOOP FOR OPTICAL ELEMENTS HAVING A TEMPERATURE-DEPENDENT RESPONSE 审中-公开
公开(公告)号：WO2022098396A8
公开(公告)日：2022-05-12
申请号：PCT/US2021/038842
申请日：2021-06-24
申请人： XILINX, INC.
发明人： CHIANG, Ping Chuan , RAJ, Mayank , XIE, Chuan , CHEN, Stanley Y. , KUMAR, Sandeep , PATTANAGIRI, Sukruth , UPADHYAYA, Parag , FRANS, Yohan
IPC分类号： H04B10/80 , H04B10/69 , H03L1/022 , H03L7/189 , H04B10/6911
摘要： Examples described herein generally relate to a temperature-locked loop for optical elements. In an example, a device includes a controller and a digital-to- analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a sheer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the sheer circuit is coupled to an output node of the DCTS. The processor has an input node coupled to an output node of the sheer circuit. The DAC has an input node coupled to an output node of the processor and is configured to be coupled to a heater. The processor is configured to control (i) the DCTS to reduce a DC component of a signal on the output node of the DCTS and (ii) an output voltage on the output node of the DAC, both based on a signal output by the sheer circuit.

2. 发明申请

WO2021252037A2 HETEROGENEOUS INTEGRATION MODULE COMPRISING THERMAL MANAGEMENT APPARATUS 审中-公开
公开(公告)号：WO2021252037A2
公开(公告)日：2021-12-16
申请号：PCT/US2021/021235
申请日：2021-03-05
申请人： XILINX, INC.
发明人： REFAI-AHMED, Gamal , RAMALINGAM, Suresh , CHANG, Ken , RAJ, Mayank , XIE, Chuan , FRANS, Yohan
IPC分类号： H01L23/367 , H01L23/40 , H01L25/16 , H01L23/473 , H01L2023/4056 , H01L2023/4075 , H01L23/3675 , H01L23/4006 , H01L25/167
摘要： Some examples described herein provide for a heterogeneous integration module (HIM) that includes a thermal management apparatus. In an example, an apparatus (e.g., a HIM) includes a wiring substrate, a first component, a second component, and a thermal management apparatus. The first component and the second component are communicatively coupled together via the wiring substrate. The thermal management apparatus is in thermal communication with the first component and the second component. The thermal management apparatus has a first thermal energy flow path for dissipating thermal energy generated by the first component and has a second thermal energy flow path for dissipating thermal energy generated by the second component. The first thermal energy flow path has a lower thermal resistivity than the second thermal energy flow path.

3. 发明申请

WO2020180621A1 METHOD AND APPARATUS FOR A PHASE LOCKED LOOP CIRCUIT 审中-公开
公开(公告)号：WO2020180621A1
公开(公告)日：2020-09-10
申请号：PCT/US2020/020187
申请日：2020-02-27
申请人： XILINX, INC.
发明人： RAJ, Mayank , TURKER MELEK, Didem, Z. , UPADHYAYA, Parag , FRANS, Yohan , CHANG, Kun-Yung
IPC分类号： H03L7/10 , H03L7/22 , H03L1/02 , H03L7/093 , H03L7/099
摘要： A phase locked loop (PLL) circuit [ 200] includes a voltage controlled oscillator (VCO) [208], a first loop circuit [220], and a second loop circuit [222], The first loop circuit includes a first loop filter [206] configured to receive a first signal [224] based on a feedback signal [218] from the VCO and provide a first VCO frequency control signal [226] to the VCO. The second loop circuit includes a compensation circuit [210] configured to receive a reference signal [218] and the first signal, and provide a second VCO frequency control signal [228] to the VCO.

4. 发明申请

WO2018182895A1 ELECTRICALLY TESTING AN OPTICAL RECEIVER 审中-公开
公开(公告)号：WO2018182895A1
公开(公告)日：2018-10-04
申请号：PCT/US2018/019728
申请日：2018-02-26
申请人： XILINX, INC.
发明人： RAJ, Mayank , FRANS, Yohan , CHANG, Kun-Yung
IPC分类号： H03K17/78 , G01R31/26
摘要： An example photodiode emulator circuit (202) includes: a first current source circuit (M1, M2, Iref); first and second transistors (M4, M5) having sources coupled together and coupled to an output of the first current source circuit, a drain of the second transistor coupled to a first node (N2); a third transistor (M7) coupled between a drain of the first transistor and a replica load circuit (302); a second current source circuit (M3, M6) coupled to the first node; a capacitor (C1) coupled between the first node and electrical ground; and a fourth transistor (M8) having a source coupled to the first node and a drain that supplies an output current.

5. 发明申请

WO2018013241A1 METHOD AND APPARATUS FOR CLOCK PHASE GENERATION 审中-公开
标题翻译：时钟相位产生的方法和装置
公开(公告)号：WO2018013241A1
公开(公告)日：2018-01-18
申请号：PCT/US2017/035236
申请日：2017-05-31
申请人： XILINX, INC.
发明人： NAMKOONG, Jinyung , RAJ, Mayank , UPADHYAYA, Parag , MANTHENA, Vamshi , HEARNE, Catherine , ERETT, Marc
IPC分类号： H03L7/099 , H03L7/24 , H03L7/08
摘要： A method, non-transitory computer readable medium, and circuit for clock phase generation are disclosed. The circuit (100) includes an injection locked oscillator (102), a loop controller (116), and a phase interpolator (108). The injection locked oscillator (102) includes an input for receiving an injected clock signal (112) and an output for forwarding a set of fixed clock phases. The loop controller (116) includes an input for receiving a phase separation error of the fixed clock phases and an output for forwarding a supply voltage derived from the phase separation error. The supply voltage matches the free running frequency of the injection locked oscillator (102) to a frequency of the injected clock signal (112). The phase interpolator (108) includes an input for receiving the set of fixed clock phases directly from the injection locked oscillator (102), an input for receiving the supply voltage from the loop controller (116), and an output for forwarding an arbitrary clock phase.
摘要翻译：公开了一种用于时钟相位产生的方法，非暂时性计算机可读介质和电路。电路（100）包括注入锁定振荡器（102），回路控制器（116）和相位内插器（108）。注入锁定振荡器（102）包括用于接收注入时钟信号（112）的输入端和用于转发一组固定时钟相位的输出端。环路控制器（116）包括用于接收固定时钟相位的相位分离误差的输入端和用于转发源自相位分离误差的电源电压的输出端。电源电压将注入锁定振荡器（102）的自由运行频率与注入的时钟信号（112）的频率相匹配。相位插值器（108）包括一个用于直接从注入锁定振荡器（102）接收一组固定时钟相位的输入端，一个用于接收来自环路控制器（116）的电源电压的输入端和一个用于转发任意时钟相。

6. 发明公开

EP3903420A1 METHOD AND APPARATUS FOR A PHASE LOCKED LOOP CIRCUIT 审中-公开
公开(公告)号：EP3903420A1
公开(公告)日：2021-11-03
申请号：EP20714072.4
申请日：2020-02-27
申请人： Xilinx, Inc.
发明人： RAJ, Mayank , TURKER MELEK, Didem, Z. , UPADHYAYA, Parag , FRANS, Yohan , CHANG, Kun-Yung
IPC分类号： H03L7/10 , H03L7/22 , H03L1/02 , H03L7/093 , H03L7/099

7. 发明申请

WO2022098396A1 TEMPERATURE LOCKED LOOP FRO OPTICAL ELEMENTS HAVING A TEMPERATURE DEPENDENT RESPONSE 审中-公开
公开(公告)号：WO2022098396A1
公开(公告)日：2022-05-12
申请号：PCT/US2021/038842
申请日：2021-06-24
申请人： XILINX, INC.
发明人： CHIANG, Ping Chuan , RAJ, Mayank , XIE, Chuan , CHEN, Stanley Y. , KUMAR, Sandeep , PATTANAGIRI, Sukruth , UPADHYAYA, Parag , FRANS, Yohan
IPC分类号： H04B10/80 , H04B10/69
摘要： Examples described herein generally relate to a temperature-locked loop for optical elements. In an example, a device includes a controller and a digital-to- analog converter (DAC). The controller includes a DC-controllable transimpedance stage (DCTS), a sheer circuit, and a processor. The DCTS is configured to be coupled to a photodiode. An input node of the sheer circuit is coupled to an output node of the DCTS. The processor has an input node coupled to an output node of the sheer circuit. The DAC has an input node coupled to an output node of the processor and is configured to be coupled to a heater. The processor is configured to control (i) the DCTS to reduce a DC component of a signal on the output node of the DCTS and (ii) an output voltage on the output node of the DAC, both based on a signal output by the sheer circuit.

8. 发明申请

WO2022066262A1 LATCH-BASED LEVEL SHIFTER CIRCUIT WITH SELF-BIASING 审中-公开
公开(公告)号：WO2022066262A1
公开(公告)日：2022-03-31
申请号：PCT/US2021/040600
申请日：2021-07-07
申请人： XILINX, INC.
发明人： RAJ, Mayank , UPADHYAYA, Parag
IPC分类号： H03K19/0185 , H04B10/516 , H04B17/18
摘要： Examples described herein generally relate to integrated circuits that include a latch-based level shifter circuit with self-biasing. In an example, an integrated circuit includes first and second latches and an output stage circuit. Each of the first and second latches includes a bias circuit electrically connected to a respective latch node and configured to provide a bias voltage at the respective latch node, which is electrically coupled to a signal input node. The output stage circuit has first and second input nodes electrically connected to first and second output nodes of the first and second latches, respectively, and a third output node. The output stage circuit is configured to responsively pull up and pull down a voltage of the third output node in response to respective voltages of the first and second input nodes.

9. 发明申请

WO2017209986A1 PHASE-LOCKED LOOP HAVING A SAMPLING PHASE DETECTOR 审中-公开
标题翻译：具有采样相检测器的锁相环
公开(公告)号：WO2017209986A1
公开(公告)日：2017-12-07
申请号：PCT/US2017/033472
申请日：2017-05-19
申请人： XILINX, INC.
发明人： RAJ, Mayank , UPADHYAYA, Parag , BEKELE, Adebabay M.
IPC分类号： H03L7/089 , H03L7/091
摘要： An example a phase-locked loop (PLL) circuit (100) includes a sampling phase detector (103) configured to receive a reference clock and a feedback clock and configured to supply a first control current and a pulse signal. The PLL further includes a charge pump (107) configured to generate a second control current based on the first control current and the pulse signal. The PLL further includes a loop filter (109) configured to filter the second control current and generate an oscillator control voltage. The PLL further includes a voltage controlled oscillator (VCO) (1 16) configured to generate an output clock based on the oscillator control voltage. The PLL further includes a frequency divider (118) configured to generate the reference clock from the output clock.
摘要翻译：一种锁相环（PLL）电路（100）的示例包括采样相位检测器（103），其被配置为接收参考时钟和反馈时钟并且被配置为提供第一控制电流和脉冲信号。 PLL还包括电荷泵（107），电荷泵（107）被配置为基于第一控制电流和脉冲信号产生第二控制电流。 PLL还包括被配置为过滤第二控制电流并生成振荡器控制电压的环路滤波器（109）。该PLL还包括被配置为基于该振荡器控制电压生成输出时钟的压控振荡器（VCO）（116）。 PLL还包括分频器（118），其被配置为从输出时钟生成参考时钟。

10. 发明申请

WO2017023529A1 CIRCUITS FOR AND METHODS OF IMPLEMENTING A DUAL-MODE OSCILLATOR 审中-公开
标题翻译：实现双模振荡器的电路和方法
公开(公告)号：WO2017023529A1
公开(公告)日：2017-02-09
申请号：PCT/US2016/042853
申请日：2016-07-18
申请人： XILINX, INC.
发明人： RAJ, Mayank , UPADHYAYA, Parag
IPC分类号： H03B5/12
CPC分类号： H03B5/124 , H03B5/1215 , H03B5/1228 , H03B5/1296 , H03B27/00 , H03B2200/0048 , H03B2200/0078
摘要： A circuit for implementing a dual-mode oscillator is disclosed. The circuit comprises a first oscillator portion (204) having a first inductor (208) coupled in parallel with a first capacitor (210) between a first node (212) and a second node (214); a first pair of output nodes (293) coupled to the first and second nodes; a second oscillator portion (206) inductively coupled to the first oscillator portion, the second oscillator portion having a second inductor (258) coupled in parallel with a second capacitor (260) between a third node (262) and a fourth node (264); a second pair of output nodes (292) coupled to the third and fourth nodes; and a control circuit (207) coupled to enable a supply of current to either the first oscillator portion (204) or the second oscillator portion (206). A method of implementing a dual-mode oscillator is also disclosed.
摘要翻译：公开了一种用于实现双模振荡器的电路。该电路包括第一振荡器部分（204），其具有与第一电容器（210）并联耦合的第一电感器（208），位于第一节点（212）和第二节点（214）之间; 耦合到第一和第二节点的第一对输出节点（293）; 电感耦合到第一振荡器部分的第二振荡器部分（206），第二振荡器部分具有与第三节点（262）和第四节点（264）之间的第二电容器（260）并联耦合的第二电感器（258） ; 耦合到第三和第四节点的第二对输出节点（292）; 以及耦合到能够向第一振荡器部分（204）或第二振荡器部分（206）提供电流的控制电路（207）。还公开了实现双模振荡器的方法。

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