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1. 发明申请

WO2017066079A1 INTERPOSER-LESS STACK DIE INTERCONNECT 审中-公开
标题翻译：无干扰的互连模块互连
公开(公告)号：WO2017066079A1
公开(公告)日：2017-04-20
申请号：PCT/US2016/055819
申请日：2016-10-06
申请人： XILINX, INC.
发明人： CHAWARE, Raghunandan , MAJUMDAR, Amitava , O'ROURKE, Glenn , SINGH, Inderjit
IPC分类号： H01L25/065 , H01L23/48 , H01L21/768 , H01L23/00
CPC分类号： H01L23/5385 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L22/14 , H01L23/3114 , H01L23/538 , H01L23/5381 , H01L23/5384 , H01L23/5386 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/92 , H01L24/94 , H01L24/96 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2221/68327 , H01L2221/68331 , H01L2221/68372 , H01L2224/03312 , H01L2224/0332 , H01L2224/0345 , H01L2224/03462 , H01L2224/12105 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/1703 , H01L2224/17051 , H01L2224/17181 , H01L2224/73204 , H01L2224/81191 , H01L2224/92 , H01L2224/94 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2924/1515 , H01L2924/152 , H01L2924/153 , H01L2924/15311 , H01L2224/03 , H01L2924/014 , H01L2924/00014 , H01L21/78 , H01L2221/68304 , H01L2224/81 , H01L21/56 , H01L21/304 , H01L2224/11 , H01L2221/68381 , H01L22/00 , H01L2224/1181
摘要： Techniques for providing a semiconductor assembly having an interconnect die (106) for die-to-die interconnection, an IC package (100), a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die (106) coupled to a first integrated circuit (IC) die (102) and a second IC die (102) by inter-die connections (108). The first interconnect die includes solid state circuitry (122) that provides a signal transmission path between the IC dice.
摘要翻译：提供一种半导体组件的技术，该半导体组件具有用于管芯间互连的互连管芯（106），IC封装（100），制造方法以及用于在IC中路由信号的方法包描述。在一个实施方式中，提供了一种半导体组件，其包括通过晶粒间连接（108）耦合到第一集成电路（IC）管芯（102）和第二IC管芯（102）的第一互连管芯（106）。第一互连裸片包括在IC裸片之间提供信号传输路径的固态电路（122）。

2. 发明申请

WO2017119937A1 STACKED SILICON PACKAGE ASSEMBLY HAVING ENHANCED STIFFENER 审中-公开
标题翻译：具有增强型加强器的堆叠硅包装组件
公开(公告)号：WO2017119937A1
公开(公告)日：2017-07-13
申请号：PCT/US2016/058788
申请日：2016-10-26
申请人： XILINX, INC.
发明人： ZOHNI, Nael , LOW, Shin S. , SINGH, Inderjit , CHAWARE, Raghunandan , HARIHARAN, Ganesh
IPC分类号： H01L23/04
CPC分类号： H01L23/16 , H01L23/562 , H01L25/065 , H01L2224/16225 , H01L2224/73204 , H01L2924/15311
摘要： A chip package assembly (100, 200, 300, 400) and method (1400) for fabricating the same are provided which utilize a stiffener (154, 254, 454, 500, 710, 810, 1110) to improve a package substrate (122) against out of plane deformation. In one example, a chip package assembly is provided that includes a package substrate, at least one integrated circuit (IC) die (114) and a stiffener. The package substrate has a first surface (102) and a second surface (104) coupled by a side wall (106). The at least one IC die is disposed on the first surface of the package substrate. The stiffener is disposed outward of the at least one IC die. The stiffener has a first surface (160) disposed outward of and bonded to the side wall of the package substrate. The stiffener has a second surface (158, 358) bonded to at least one of the first and second surfaces (102, 104) of the package substrate.
摘要翻译：提供了一种芯片封装组件（100,200,300,400）和用于制造该芯片封装组件（100,200,300,400）和方法（1400），其利用加强件（154,254,454,500,710,810,1110 ）以改善封装衬底（122）的平面外变形。在一个示例中，提供了一种芯片封装组件，其包括封装衬底，至少一个集成电路（IC）管芯（114）和加强件。封装衬底具有由侧壁（106）耦合的第一表面（102）和第二表面（104）。至少一个IC管芯设置在封装基板的第一表面上。加强件设置在至少一个IC管芯的外部。加强件具有第一表面（160），第一表面（160）设置在封装基板的侧壁的外侧并与其结合。加强件具有结合到封装衬底的第一和第二表面（102,104）中的至少一个的第二表面（158,358）。

3. 发明申请

WO2013119309A1 STACKED DIE ASSEMBLY WITH MULTIPLE INTERPOSERS 审中-公开
标题翻译：堆叠式电池组件与多个插座
公开(公告)号：WO2013119309A1
公开(公告)日：2013-08-15
申请号：PCT/US2012/067543
申请日：2012-12-03
申请人： XILINX, INC.
发明人： WU, Ephrem, C. , BANIJAMALI, Bahareh , CHAWARE, Raghunandan
IPC分类号： H01L25/065 , H01L23/14 , H01L23/498 , H01L23/538
CPC分类号： H01L25/0652 , H01L23/147 , H01L23/5384 , H01L23/5385 , H01L25/18 , H01L2224/16145 , H01L2224/16225 , H01L2924/15151 , H01L2924/15192 , H01L2924/15311 , H01L2924/157
摘要： A stacked die assembly for an IC includes a first interposer (500A); a second interposer (500B); a first integrated circuit die (300, 1110), a second integrated circuit die (303), and a plurality of components (713). The first integrated circuit die (300, 1110) is interconnected to the first interposer (500A) and the second interposer (500B), and the second integrated circuit die (303) is interconnected to the second interposer (500B). The plurality of components (713) interconnect the first integrated circuit die (300, 1110) to the first interposer (500A) and the second interposer (500B). Signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components. In some exemplary assemblies, the plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area (710) of the first interposer and the second interposer, and signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components, avoiding the interconnect restricted area of the first interposer and the second interposer. Methods of forming these assemblies are also described.
摘要翻译：一种用于IC的堆叠式芯片组件，包括：第一插入件（500A）; 第二插入器（500B）; 第一集成电路管芯（300,1110），第二集成电路管芯（303）和多个部件（713）。第一集成电路管芯（300,1110）与第一插入件（500A）和第二插入件（500B）互连，第二集成电路管芯（303）与第二插入件（500B）互连。多个部件（713）将第一集成电路管芯（300,1110）与第一插入件（500A）和第二插入件（500B）互连。信号经由第一集成电路管芯和多个部件在第一插入器和第二插入器之间布线。在一些示例性组件中，将第一集成电路管芯与第一插入件和第二插入件互连的多个部件位于第一插入器和第二插入器的互连限制区域（710）的外部，并且信号在第一内插器插入器和第二插入器，经由第一集成电路管芯和多个部件，避免了第一插入件和第二插入件的互连限制区域。还描述了形成这些组件的方法。

4. 发明公开

EP3363048A1 INTERPOSER-LESS STACK DIE INTERCONNECT 审中-公开
公开(公告)号：EP3363048A1
公开(公告)日：2018-08-22
申请号：EP16785621.0
申请日：2016-10-06
申请人： Xilinx, Inc.
发明人： CHAWARE, Raghunandan , MAJUMDAR, Amitava , O'ROURKE, Glenn , SINGH, Inderjit
IPC分类号： H01L25/065 , H01L23/48 , H01L21/768 , H01L23/00
CPC分类号： H01L23/5385 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L22/14 , H01L23/3114 , H01L23/538 , H01L23/5381 , H01L23/5383 , H01L23/5384 , H01L23/5386 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/16 , H01L24/17 , H01L24/81 , H01L24/92 , H01L24/94 , H01L24/96 , H01L25/0652 , H01L25/0655 , H01L25/18 , H01L2221/68327 , H01L2221/68331 , H01L2221/68372 , H01L2224/03312 , H01L2224/0332 , H01L2224/0345 , H01L2224/03462 , H01L2224/12105 , H01L2224/131 , H01L2224/16145 , H01L2224/16227 , H01L2224/1703 , H01L2224/17051 , H01L2224/17181 , H01L2224/73204 , H01L2224/81191 , H01L2224/92 , H01L2224/94 , H01L2924/14 , H01L2924/1431 , H01L2924/1434 , H01L2924/1461 , H01L2924/1515 , H01L2924/152 , H01L2924/153 , H01L2924/15311 , H01L2224/03 , H01L2924/014 , H01L2924/00014 , H01L21/78 , H01L2221/68304 , H01L2224/81 , H01L21/56 , H01L21/304 , H01L2224/11 , H01L2221/68381 , H01L22/00 , H01L2224/1181
摘要： Techniques for providing a semiconductor assembly having an interconnect die for die-to-die interconnection, an IC package, a method for manufacturing, and a method for routing signals in an IC package are described. In one implementation, a semiconductor assembly is provided that includes a first interconnect die coupled to a first integrated circuit (IC) die and a second IC die by inter-die connections. The first interconnect die includes solid state circuitry that provides a signal transmission path between the IC dice.

5. 发明公开

EP3357085A1 STACKED SILICON PACKAGE ASSEMBLY HAVING ENHANCED STIFFENER 审中-公开
公开(公告)号：EP3357085A1
公开(公告)日：2018-08-08
申请号：EP16794822.3
申请日：2016-10-26
申请人： Xilinx, Inc.
发明人： ZOHNI, Nael , LOW, Shin S. , SINGH, Inderjit , CHAWARE, Raghunandan , HARIHARAN, Ganesh
IPC分类号： H01L23/04
CPC分类号： H01L23/16 , H01L23/562 , H01L25/065 , H01L2224/16225 , H01L2224/73204 , H01L2924/15311
摘要： A chip package assembly (100, 200, 300, 400) and method (1400) for fabricating the same are provided which utilize a stiffener (154, 254, 454, 500, 710, 810, 1110) to improve a package substrate (122) against out of plane deformation. In one example, a chip package assembly is provided that includes a package substrate, at least one integrated circuit (IC) die (114) and a stiffener. The package substrate has a first surface (102) and a second surface (104) coupled by a side wall (106). The at least one IC die is disposed on the first surface of the package substrate. The stiffener is disposed outward of the at least one IC die. The stiffener has a first surface (160) disposed outward of and bonded to the side wall of the package substrate. The stiffener has a second surface (158, 358) bonded to at least one of the first and second surfaces (102, 104) of the package substrate.

6. 发明公开

EP2812919A1 STACKED DIE ASSEMBLY WITH MULTIPLE INTERPOSERS 审中-公开
标题翻译： GESTAPELTE ANORDNUNG MIT MEHREREN ZWISCHENGLIEDERN
公开(公告)号：EP2812919A1
公开(公告)日：2014-12-17
申请号：EP12816386.2
申请日：2012-12-03
申请人： Xilinx, Inc.
发明人： WU, Ephrem, C. , BANIJAMALI, Bahareh , CHAWARE, Raghunandan
IPC分类号： H01L25/065 , H01L23/14 , H01L23/498 , H01L23/538
CPC分类号： H01L25/0652 , H01L23/147 , H01L23/5384 , H01L23/5385 , H01L25/18 , H01L2224/16145 , H01L2224/16225 , H01L2924/15151 , H01L2924/15192 , H01L2924/15311 , H01L2924/157
摘要： A stacked die assembly for an IC includes a first interposer (500A); a second interposer (500B); a first integrated circuit die (300, 1110), a second integrated circuit die (303), and a plurality of components (713). The first integrated circuit die (300, 1110) is interconnected to the first interposer (500A) and the second interposer (500B), and the second integrated circuit die (303) is interconnected to the second interposer (500B). The plurality of components (713) interconnect the first integrated circuit die (300, 1110) to the first interposer (500A) and the second interposer (500B). Signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components. In some exemplary assemblies, the plurality of components that interconnect the first integrated circuit die to the first interposer and the second interposer are located outside an interconnect restricted area (710) of the first interposer and the second interposer, and signals are routed between the first interposer and the second interposer via the first integrated circuit die and the plurality of components, avoiding the interconnect restricted area of the first interposer and the second interposer. Methods of forming these assemblies are also described.
摘要翻译：一种用于IC的堆叠式芯片组件包括第一插入件（500A）; 第二插入器（500B）; 第一集成电路管芯（300,1110），第二集成电路管芯（303）和多个部件（713）。第一集成电路管芯（300,1110）与第一插入件（500A）和第二插入件（500B）互连，第二集成电路管芯（303）与第二插入件（500B）互连。多个部件（713）将第一集成电路管芯（300,1110）与第一插入件（500A）和第二插入件（500B）互连。信号经由第一集成电路管芯和多个部件在第一插入器和第二插入器之间布线。在一些示例性组件中，将第一集成电路管芯与第一插入器和第二插入器互连的多个部件位于第一插入器和第二插入器的互连受限区域（710）的外部，并且信号在第一插入器和第二插入器，经由第一集成电路管芯和多个部件，避免了第一插入件和第二插入件的互连限制区域。还描述了形成这些组件的方法。

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