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    • 8. 发明授权
    • Method and integrated circuit for increasing the immunity to interference
    • 用于增加抗干扰性的方法和集成电路
    • US08578258B2
    • 2013-11-05
    • US10590087
    • 2005-02-17
    • Wolfgang FeyMicha HeinzAdrian TraskovFrank Michel
    • Wolfgang FeyMicha HeinzAdrian TraskovFrank Michel
    • G06F11/00
    • G06F11/0772G06F11/0724G06F11/0736G06F11/0739G06F11/1645G06F11/2215
    • Disclosed is a method of improving the immunity to interference of an integrated circuit (16) having error signals transferred between a microprocessor chip or multiple processor μC (1) and an additional component (2). For the transfer, a minimum pulse length that is independent of the clock frequency of the microprocessor or the microprocessors is defined, starting from which a signal on an error line having a defined pulse length is interpreted as an error. Also disclosed is an integrated circuit, which is designed so that the above method is implemented. The circuit has a microprocessor chip or multiple processor microcontroller (1) or microprocessor module and an additional component (2) having separately arranged power elements. The circuit also has pulse extending devices and/or signal delaying devices for the output of error pulses (6, 6′) one after the other through at least one error line (3, 4).
    • 公开了一种提高在微处理器芯片或多处理器muC(1)与附加部件(2)之间传送的误差信号的集成电路(16)的抗干扰性的方法。 对于传输,定义了与微处理器或微处理器的时钟频率无关的最小脉冲长度,从而将具有定义的脉冲长度的误差线上的信号从该脉冲长度解释为误差。 还公开了一种集成电路,其被设计为实现上述方法。 该电路具有微处理器芯片或多处理器微控制器(1)或微处理器模块以及具有单独布置的功率元件的附加组件(2)。 电路还具有脉冲延伸装置和/或信号延迟装置,用于通过至少一个误差线(3,4)一个接一个地输出误差脉冲(6,6')。