专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08313987B2 Anti-fuse memory cell 有权
标题翻译：防熔丝存储单元
公开(公告)号：US08313987B2
公开(公告)日：2012-11-20
申请号：US13219215
申请日：2011-08-26
申请人： Wlodek Kurjanowicz , Steven Smith
发明人： Wlodek Kurjanowicz , Steven Smith
IPC分类号： H01L21/82
CPC分类号： G11C17/16 , H01L23/5252 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse memory cell having a variable thickness gate dielectric. The variable thickness dielectric has a thick portion and a thin portion, where the thin portion has at least one dimension less than a minimum feature size of a process technology. The thin portion can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate dielectric substantially identical in thickness to the thick portion of the variable thickness gate dielectric of the anti-fuse transistor.
摘要翻译：具有可变厚度栅极电介质的反熔丝存储单元。可变厚度电介质具有厚部分和薄部分，其中薄部分具有小于工艺技术的最小特征尺寸的至少一个尺寸。薄部分的形状可以是矩形或三角形。反熔丝晶体管可以用于具有存取晶体管的双晶体管存储单元，栅极电介质的厚度基本上与反熔丝晶体管的可变厚度栅极电介质的厚部相同。

2. 发明授权

US07764532B2 High speed OTP sensing scheme 有权
标题翻译：高速OTP感应方案
公开(公告)号：US07764532B2
公开(公告)日：2010-07-27
申请号：US12389933
申请日：2009-02-20
申请人： Wlodek Kurjanowicz , Steven Smith
发明人： Wlodek Kurjanowicz , Steven Smith
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , H01L21/28211 , H01L23/5252 , H01L27/10 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.
摘要翻译：公开了一种用于非易失性存储器阵列的高速感测方案。存储器阵列包括以互补位线配置布置的非易失性存储单元，包括用于将位线预充电到诸如VSS的第一电压电平的预充电电路，用于在补充位线对的参考位线上施加参考电荷的参考电路，以及位线用于感测互补位线对之间的电压差的读出放大器。当连接到激活的字线的编程的非易失性存储器单元将字线电压耦合到数据位线时，数据位线上的电压被改变。

3. 发明申请

US20070165441A1 HIGH SPEED OTP SENSING SCHEME 有权
标题翻译：高速OTP感应方案
公开(公告)号：US20070165441A1
公开(公告)日：2007-07-19
申请号：US11618330
申请日：2006-12-29
申请人： Wlodek Kurjanowicz , Steven Smith
发明人： Wlodek Kurjanowicz , Steven Smith
IPC分类号： G11C7/00 , G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , H01L21/28211 , H01L23/5252 , H01L27/10 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.
摘要翻译：公开了一种用于非易失性存储器阵列的高速感测方案。存储器阵列包括以互补位线配置布置的非易失性存储单元，包括用于将位线预充电到诸如VSS的第一电压电平的预充电电路，用于在补充位线对的参考位线上施加参考电荷的参考电路，以及位线用于感测互补位线对之间的电压差的读出放大器。当连接到激活的字线的编程的非易失性存储器单元将字线电压耦合到数据位线时，数据位线上的电压被改变。

4. 发明授权

US07755162B2 Anti-fuse memory cell 有权
标题翻译：防熔丝存储单元
公开(公告)号：US07755162B2
公开(公告)日：2010-07-13
申请号：US11762552
申请日：2007-06-13
申请人： Wlodek Kurjanowicz , Steven Smith
发明人： Wlodek Kurjanowicz , Steven Smith
IPC分类号： H01L29/00
CPC分类号： G11C17/16 , H01L23/5252 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor.
摘要翻译：具有可变厚度栅极氧化物的反熔丝存储单元。可变厚栅极氧化物具有厚的栅极氧化物部分和薄的栅极氧化物部分，其中栅极氧化物部分具有小于工艺技术的最小特征尺寸的至少一个尺寸。薄栅氧化物的形状可以是矩形或三角形。反熔丝晶体管可以用于具有存取晶体管的双晶体管存储单元，栅极氧化物的厚度与抗熔丝晶体管的可变厚栅极氧化物的厚栅极氧化物的厚度基本相同。

5. 发明授权

US08767433B2 Methods for testing unprogrammed OTP memory 有权
标题翻译：测试未编程OTP内存的方法
公开(公告)号：US08767433B2
公开(公告)日：2014-07-01
申请号：US13412500
申请日：2012-03-05
申请人： Wlodek Kurjanowicz , Steven Smith
发明人： Wlodek Kurjanowicz , Steven Smith
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , G11C29/027 , H01L21/28211 , H01L23/5252 , H01L27/10 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Methods for testing unprogrammed single transistor and two transistor anti-fuse memory cells include testing for connections of the cells to a bitline by comparing a voltage characteristic of a bitline connected to the cell under test to a reference bitline having a predetermined voltage characteristic. Some methods can use test cells having an access transistor identically configured to the access transistor of a normal memory cell, but omitting the anti-fuse device found in the normal memory cell, for testing the presence of a connection of the normal memory cell to the bitline. Such a test cell can be used in a further test for determining the level of capacitive coupling of the wordline voltage to the bitlines relative to that of a normal memory cell under test.
摘要翻译：用于测试未编程单晶体管和两晶体管反熔丝存储单元的方法包括通过将连接到被测电池的位线的电压特性与具有预定电压特性的参考位线进行比较来测试单元与位线的连接。一些方法可以使用具有与正常存储器单元的存取晶体管相同配置的存取晶体管的测试单元，但是省略在正常存储单元中发现的反熔丝器件，用于测试正常存储器单元与位线这样的测试单元可用于进一步测试，用于确定字线电压与位线相对于正在测试的正常存储器单元的电容耦合水平。

6. 发明授权

US08026574B2 Anti-fuse memory cell 有权
标题翻译：防熔丝存储单元
公开(公告)号：US08026574B2
公开(公告)日：2011-09-27
申请号：US12814124
申请日：2010-06-11
申请人： Wlodek Kurjanowicz , Steven Smith
发明人： Wlodek Kurjanowicz , Steven Smith
IPC分类号： H01L29/00
CPC分类号： G11C17/16 , H01L23/5252 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor.
摘要翻译：具有可变厚度栅极氧化物的反熔丝存储单元。可变厚栅极氧化物具有厚的栅极氧化物部分和薄的栅极氧化物部分，其中栅极氧化物部分具有小于工艺技术的最小特征尺寸的至少一个尺寸。薄栅氧化物的形状可以是矩形或三角形。反熔丝晶体管可以用于具有存取晶体管的双晶体管存储单元，栅极氧化物的厚度与抗熔丝晶体管的可变厚栅极氧化物的厚栅极氧化物的厚度基本相同。

7. 发明授权

US07511982B2 High speed OTP sensing scheme 有权
标题翻译：高速OTP感应方案
公开(公告)号：US07511982B2
公开(公告)日：2009-03-31
申请号：US11618330
申请日：2006-12-29
申请人： Wlodek Kurjanowicz , Steven Smith
发明人： Wlodek Kurjanowicz , Steven Smith
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , H01L21/28211 , H01L23/5252 , H01L27/10 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.
摘要翻译：公开了一种用于非易失性存储器阵列的高速感测方案。存储器阵列包括以互补位线配置布置的非易失性存储单元，包括用于将位线预充电到诸如VSS的第一电压电平的预充电电路，用于在补充位线对的参考位线上施加参考电荷的参考电路，以及位线用于感测互补位线对之间的电压差的读出放大器。当连接到激活的字线的编程的非易失性存储器单元将字线电压耦合到数据位线时，数据位线上的电压被改变。

8. 发明授权

US08130532B2 High speed OTP sensing scheme 有权
标题翻译：高速OTP感应方案
公开(公告)号：US08130532B2
公开(公告)日：2012-03-06
申请号：US12822332
申请日：2010-06-24
申请人： Wlodek Kurjanowicz , Steven Smith
发明人： Wlodek Kurjanowicz , Steven Smith
IPC分类号： G11C17/00
CPC分类号： G11C17/16 , G11C17/18 , H01L21/28211 , H01L23/5252 , H01L27/10 , H01L27/101 , H01L27/112 , H01L27/11206 , H01L29/42368 , H01L29/4238 , H01L29/42384 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.
摘要翻译：公开了一种用于非易失性存储器阵列的高速感测方案。存储器阵列包括以互补位线配置布置的非易失性存储单元，包括用于将位线预充电到诸如VSS的第一电压电平的预充电电路，用于在补充位线对的参考位线上施加参考电荷的参考电路，以及位线用于感测互补位线对之间的电压差的读出放大器。当连接到激活的字线的编程的非易失性存储器单元将字线电压耦合到数据位线时，数据位线上的电压被改变。

9. 发明授权

US07944727B2 Mask programmable anti-fuse architecture 有权
标题翻译：面罩可编程反熔丝架构
公开(公告)号：US07944727B2
公开(公告)日：2011-05-17
申请号：US12306114
申请日：2007-12-20
申请人： Wlodek Kurjanowicz
发明人： Wlodek Kurjanowicz
IPC分类号： G11C17/00
CPC分类号： G11C17/18 , G11C17/10 , H01L27/0203 , H01L27/112
摘要： A memory array having both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. All memory cells of the memory array are configured as one-time programmable memory cells. Any number of these one-time programmable memory cells are convertible into mask programmable memory cells through mask programming, such as diffusion mask programming or contact/via mask programming. Manufacturing of such a hybrid memory array is simplified because both types of memory cells are constructed of the same materials, therefore only one common set of manufacturing process steps is required. Inadvertent user programming of the mask programmable memory cells is inhibited by a programming lock circuit.
摘要翻译：具有连接到字线和位线的掩模可编程和一次性可编程存储器单元的存储器阵列。存储器阵列的所有存储单元被配置为一次性可编程存储器单元。任何数量的这些一次性可编程存储器单元通过掩模编程（例如扩散掩模编程或接触/通孔掩模编程）可转换成掩模可编程存储器单元。这种混合存储器阵列的制造被简化，因为两种类型的存储器单元由相同的材料构成，因此仅需要一组常规的制造工艺步骤。掩模可编程存储单元的无意的用户编程被编程锁定电路所禁止。

10. 发明授权

US07940595B2 Power up detection system for a memory device 有权
标题翻译：用于存储设备的上电检测系统
公开(公告)号：US07940595B2
公开(公告)日：2011-05-10
申请号：US12306940
申请日：2007-12-20
申请人： Wlodek Kurjanowicz
发明人： Wlodek Kurjanowicz
IPC分类号： G11C7/00
CPC分类号： G11C29/52 , G11C5/143 , G11C16/3454 , G11C16/3459 , G11C17/14 , G11C17/16 , G11C17/165 , G11C19/00 , G11C29/027 , G11C2029/0407
摘要： A power up detection system for a memory device. Two rows of memory cells are mask programmed to include a word of data having an arbitrary size. The word in the second row is a single-bit shifted version of the word in the first row, such that each bit is shifted one bit position in a predetermined direction. The bits of the first word are read from the first row into slave latches of the register stages of a data register, and then shifted into the master latches of the next register stage of the data register. The bits of the second word are read from the second row into the slave latches of the register stages. Data comparison logic compares data stored in the master and slave latches of each register stage, and provides a signal indicating matching data between the first latches and the second latches, thereby indicating successful power up of the memory device.
摘要翻译：用于存储器件的上电检测系统。两行存储器单元被编程为包括具有任意大小的数据字。第二行中的字是第一行中单词的单位移位版本，使得每个位沿预定方向移位一位位置。第一个字的位从第一行读取到数据寄存器的寄存器级的从锁存器，然后移入数据寄存器的下一个寄存器级的主锁存器。第二个字的位从第二行读入寄存器级的从锁存器。数据比较逻辑比较存储在每个寄存器级的主锁存器和从锁存器中的数据，并且提供指示第一锁存器和第二锁存器之间的匹配数据的信号，从而指示存储器件的成功上电。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式