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1. 发明授权

US07353438B2 Transparent error correcting memory 失效
标题翻译：透明错误纠正内存
公开(公告)号：US07353438B2
公开(公告)日：2008-04-01
申请号：US10645861
申请日：2003-08-20
申请人： Wingyu Leung , Kit Sang Tam , Mikolaj Tworek , Fu-Chieh Hsu
发明人： Wingyu Leung , Kit Sang Tam , Mikolaj Tworek , Fu-Chieh Hsu
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory interface and an error detection/correction unit. The memory array is configured to store test data patterns and corresponding error correction code (ECC) values. The memory interface is configured such that the ECC values are not directly accessible. The error detection/correction unit is configured to correct single-bit errors in the test data patterns and corresponding ECC values. A set of test data patterns associated with the semiconductor memory is selected such that any multiple-bit error in a test data pattern and the corresponding ECC value causes the error detection/correction unit to provide an output data pattern having an error, thereby rendering multiple-bit faults 100% detectable.
摘要翻译：具有透明误差校正电路的存储器系统为测试数据模式和相应的纠错码（ECC）值提供完全卡住的故障覆盖。存储器系统包括具有存储器阵列，存储器接口和错误检测/校正单元的半导体存储器。存储器阵列被配置为存储测试数据模式和相应的纠错码（ECC）值。存储器接口被配置为使得ECC值不能直接访问。错误检测/校正单元被配置为校正测试数据模式中的单位错误和对应的ECC值。选择与半导体存储器相关联的一组测试数据模式，使得测试数据模式中的任何多位错误和相应的ECC值导致错误检测/校正单元提供具有错误的输出数据模式，从而渲染多个位错误100％可检测。

2. 发明申请

US20050044467A1 Transparent error correcting memory 失效
标题翻译：透明错误纠正内存
公开(公告)号：US20050044467A1
公开(公告)日：2005-02-24
申请号：US10645861
申请日：2003-08-20
申请人： Wingyu Leung , Kit Tam , Mikolaj Tworek , Fu-Chieh Hsu
发明人： Wingyu Leung , Kit Tam , Mikolaj Tworek , Fu-Chieh Hsu
IPC分类号： G06F11/10 , G11C29/00 , H03M13/00
CPC分类号： G06F11/1048
摘要： A memory system with transparent error correction circuitry provides full stuck-at fault coverage for both test data patterns and the corresponding error correction code (ECC) values. The memory system includes a semiconductor memory having a memory array, a memory interface and an error detection/correction unit. The memory array is configured to store test data patterns and corresponding error correction code (ECC) values. The memory interface is configured such that the ECC values are not directly accessible. The error detection/correction unit is configured to correct single-bit errors in the test data patterns and corresponding ECC values. A set of test data patterns associated with the semiconductor memory is selected such that any multiple-bit error in a test data pattern and the corresponding ECC value causes the error detection/correction unit to provide an output data pattern having an error, thereby rendering multiple-bit faults 100% detectable.
摘要翻译：具有透明误差校正电路的存储器系统为测试数据模式和相应的纠错码（ECC）值提供完全卡住的故障覆盖。存储系统包括具有存储器阵列，存储器接口和错误检测/校正单元的半导体存储器。存储器阵列被配置为存储测试数据模式和相应的纠错码（ECC）值。存储器接口被配置为使得ECC值不能直接访问。错误检测/校正单元被配置为校正测试数据模式中的单位错误和对应的ECC值。选择与半导体存储器相关联的一组测试数据模式，使得测试数据模式中的任何多位错误和相应的ECC值导致错误检测/校正单元提供具有错误的输出数据模式，从而渲染多个位错误100％可检测。

3. 发明授权

US5787267A Caching method and circuit for a memory system with circuit module architecture 失效
标题翻译：具有电路模块架构的存储器系统的缓存方法和电路
公开(公告)号：US5787267A
公开(公告)日：1998-07-28
申请号：US479915
申请日：1995-06-07
申请人： Wingyu Leung , Kit Sang Tam
发明人： Wingyu Leung , Kit Sang Tam
IPC分类号： G06F12/02 , G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0215 , G06F12/0893 , G06F12/084
摘要： A structure and method of implementing a cache memory for a multi-processor system. The cache memory includes a main memory which is coupled to a main memory bus. A plurality of processors can also be coupled to the main memory bus. The main memory includes a plurality of RAM circuit module memory banks. The sense amplifiers of a predetermined number of banks are used as cache memory (i.e., sense amplifier cache lines). The number of banks used with sense amplifiers activated is substantially less than the total number of banks. The banks which are not used as cache memory are kept in a precharged state.
摘要翻译：实现用于多处理器系统的高速缓冲存储器的结构和方法。高速缓冲存储器包括耦合到主存储器总线的主存储器。多个处理器也可以耦合到主存储器总线。主存储器包括多个RAM电路模块存储体。将预定数量的存储体的读出放大器用作高速缓冲存储器（即，读出放大器高速缓存行）。激活的读出放大器使用的存储体数量远远少于银行总数。不用作高速缓冲存储器的存储体保持在预充电状态。

4. 发明授权

US07392456B2 Predictive error correction code generation facilitating high-speed byte-write in a semiconductor memory 有权
标题翻译：在半导体存储器中促进高速字节写入的预测性纠错码产生
公开(公告)号：US07392456B2
公开(公告)日：2008-06-24
申请号：US10997604
申请日：2004-11-23
申请人： Wingyu Leung , Kit Sang Tam
发明人： Wingyu Leung , Kit Sang Tam
IPC分类号： G11C29/00
CPC分类号： G11C7/1006 , G06F11/1056 , G11C11/4078
摘要： Write check bits are generated in a predictive manner for partial-word write transactions in a memory system implementing error code correction. A read data word and associated read check bits are read from an address of the memory. If an error exists in a byte of the read data word, this byte is identified. At the same time, one or more bytes of the uncorrected read data word are merged with one or more bytes of a write data word, thereby creating a merged data word. Write check bits are generated in response to the merged data word. If the merged data word includes a byte of the read data word, which contains an error, the write check bits are modified to reflect this error. The merged data word and the modified (or unmodified) write check bits are then written to the address of the memory.
摘要翻译：以实现错误代码校正的存储器系统中的部分字写入事务的预测方式生成写校验位。从存储器的地址读取读取数据字和相关联的读取校验位。如果读取数据字的一个字节存在错误，则识别该字节。同时，未校正的读取数据字的一个或多个字节与写入数据字的一个或多个字节合并，从而创建合并的数据字。响应于合并的数据字生成写校验位。如果合并的数据字包含包含错误的读取数据字的字节，则修改校验位以反映该错误。合并的数据字和修改的（或未修改的）写入校验位然后被写入存储器的地址。

5. 发明授权

US6000007A Caching in a multi-processor computer system 失效
标题翻译：在多处理器计算机系统中缓存
公开(公告)号：US6000007A
公开(公告)日：1999-12-07
申请号：US80893
申请日：1998-05-18
申请人： Wingyu Leung , Kit Sang Tam
发明人： Wingyu Leung , Kit Sang Tam
IPC分类号： G06F12/02 , G06F12/08 , G06F12/00 , G11C8/00
CPC分类号： G06F12/0862 , G06F12/0215 , G06F12/0893 , G06F12/084
摘要： A structure and method of implementing a cache memory for a multi-processor system. The cache memory includes a main memory which is coupled to a main memory bus. A plurality of processors can also be coupled to the main memory bus. The main memory includes a plurality of RAM circuit module memory banks. The sense amplifiers of a predetermined number of banks are used as cache memory (i.e., sense amplifier cache lines). The number of banks used with sense amplifiers activated is substantially less than the total number of banks. The banks which are not used as cache memory are kept in a precharged state.
摘要翻译：实现用于多处理器系统的高速缓冲存储器的结构和方法。高速缓冲存储器包括耦合到主存储器总线的主存储器。多个处理器也可以耦合到主存储器总线。主存储器包括多个RAM电路模块存储体。将预定数量的存储体的读出放大器用作高速缓存存储器（即，读出放大器高速缓存行）。激活的读出放大器使用的存储体数量远远少于银行总数。不用作高速缓冲存储器的存储体保持在预充电状态。

6. 发明授权

US07206913B2 High speed memory system 有权
标题翻译：高速存储系统
公开(公告)号：US07206913B2
公开(公告)日：2007-04-17
申请号：US10927157
申请日：2004-08-25
申请人： Fu-Chieh Hsu , Wingyu Leung
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G06F12/00
CPC分类号： G06F12/0893 , G06F12/0855 , G06F12/0879 , G06F12/0897 , G06F12/10 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/406 , G11C11/4076 , G11C11/4096
摘要： A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, precharging of the DRAM array is transparent to the CPU bus.
摘要翻译：一种用于在计算机系统中实现DRAM存储器阵列作为第二级高速缓冲存储器的方法和结构。计算机系统包括中央处理单元（CPU），第一级SRAM缓存存储器，耦合到CPU的CPU总线以及包括与CPU总线耦合的DRAM阵列的第二级高速缓冲存储器。当访问DRAM阵列时，以自定时的异步方式执行行访问和列解码操作。然后以相对于时钟信号的同步方式执行列选择操作的预定序列。向DRAM阵列提供加宽的数据路径，有效地增加DRAM阵列的数据速率。通过以比CPU总线更高的数据速率操作DRAM阵列，为DRAM阵列预充电提供了额外的时间。因此，DRAM阵列的预充电对于CPU总线是透明的。

7. 发明申请

US20050027929A1 High speed memory system 有权
标题翻译：高速存储系统
公开(公告)号：US20050027929A1
公开(公告)日：2005-02-03
申请号：US10927157
申请日：2004-08-25
申请人： Fu-Chieh Hsu , Wingyu Leung
发明人： Fu-Chieh Hsu , Wingyu Leung
IPC分类号： G06F12/00 , G06F12/06 , G06F12/08
CPC分类号： G06F12/0893 , G06F12/0855 , G06F12/0879 , G06F12/0897 , G06F12/10 , G11C7/10 , G11C7/1018 , G11C7/1051 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C11/406 , G11C11/4076 , G11C11/4096
摘要： A method and structure for implementing a DRAM memory array as a second level cache memory in a computer system. The computer system includes a central processing unit (CPU), a first level SRAM cache memory, a CPU bus coupled to the CPU, and second level cache memory which includes a DRAM array coupled to the CPU bus. When accessing the DRAM array, row access and column decoding operations are performed in a self-timed asynchronous manner. Predetermined sequences of column select operations are then performed in a synchronous manner with respect to a clock signal. A widened data path is provided to the DRAM array, effectively increasing the data rate of the DRAM array. By operating the DRAM array at a higher data rate than the CPU bus, additional time is provided for precharging the DRAM array. As a result, precharging of the DRAM array is transparent to the CPU bus.
摘要翻译：一种用于在计算机系统中实现DRAM存储器阵列作为第二级高速缓冲存储器的方法和结构。计算机系统包括中央处理单元（CPU），第一级SRAM缓存存储器，耦合到CPU的CPU总线以及包括与CPU总线耦合的DRAM阵列的第二级高速缓冲存储器。当访问DRAM阵列时，以自定时的异步方式执行行访问和列解码操作。然后以相对于时钟信号的同步方式执行列选择操作的预定序列。向DRAM阵列提供加宽的数据路径，有效地增加了DRAM阵列的数据速率。通过以比CPU总线更高的数据速率操作DRAM阵列，为DRAM阵列预充电提供了额外的时间。因此，DRAM阵列的预充电对于CPU总线是透明的。

8. 发明授权

US06754746B1 Memory array with read/write methods 失效
标题翻译：具有读/写方式的内存数组
公开(公告)号：US06754746B1
公开(公告)日：2004-06-22
申请号：US09535656
申请日：2000-03-23
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G06F1300
CPC分类号： H04L25/026 , G06F13/40 , G06F13/4072 , G06F13/4077
摘要： Improved circuitry for connecting the memory array to a data bus allows for high speed accessing of the memory array. Sense amplifier latches are coupled to each column of memory cells. The latched sense amplifiers are coupled to decoders which, in turn, are coupled to data amplifiers. The data amplifiers are coupled to a data bus. Data being read from or written to the memory cells is via the sense amplifier latches, the decoders, and data amplifiers.
摘要翻译：用于将存储器阵列连接到数据总线的改进的电路允许存储器阵列的高速存取。读出放大器锁存器耦合到每列存储器单元。锁存的读出放大器耦合到解码器，解码器又耦合到数据放大器。数据放大器耦合到数据总线。通过读出放大器锁存器，解码器和数据放大器读取或写入存储器单元的数据。

9. 发明授权

US06509595B1 DRAM cell fabricated using a modified logic process and method for operating same 失效
标题翻译：使用改进的逻辑处理和操作方法制造的DRAM单元
公开(公告)号：US06509595B1
公开(公告)日：2003-01-21
申请号：US09427383
申请日：1999-10-25
申请人： Wingyu Leung , Fu-Chieh Hsu
发明人： Wingyu Leung , Fu-Chieh Hsu
IPC分类号： H01L31119
CPC分类号： H01L27/10852 , G11C5/147 , G11C8/08 , G11C11/4074 , G11C11/4085 , G11C2207/104 , H01L27/1085 , H01L27/10873 , H01L28/91
摘要： A memory system that includes a dynamic random access memory (DRAM) cell that includes an access transistor and a storage capacitor. The storage capacitor of the DRAM cell is fabricated by forming a polysilicon crown electrode, a dielectric layer overlying the polysilicon crown, and a polysilicon plate electrode overlying the dielectric layer. A first set of thermal cycles are performed during the formation of the storage capacitor to form and anneal the elements of the capacitor structure. After the first set of thermal cycles are complete, shallow P+ and/or N+ regions are formed by ion implantation, and metal salicide is formed. As a result, the relatively high first set of thermal cycles required to form the capacitor structure does not adversely affect the shallow P+ and N+ regions or the metal salicide. A second set of thermal cycles, which are comparable to or less than the first set of thermal cycles, are performed during the formation of the shallow regions and the metal salicide. The DRAM cell is operated in response to a word line driver that is controlled to provide a positive boosted voltage and a negative boosted voltage to the word line, thereby controlling access to the DRAM cell. The positive boosted voltage is greater than Vdd but less than Vdd plus the absolute value of a transistor threshold voltage Vt. Similarly, the negative boosted voltage generator is less than VSS by an amount less than Vt.
摘要翻译：一种包括动态随机存取存储器（DRAM）单元的存储器系统，其包括存取晶体管和存储电容器。 DRAM单元的存储电容器通过形成多晶硅冠状电极，覆盖多晶硅冠的电介质层和覆盖在电介质层上的多晶硅板电极来制造。在形成存储电容器期间执行第一组热循环以形成和退火电容器结构的元件。在第一组热循环完成后，通过离子注入形成浅的P +和/或N +区，形成金属硅化物。结果，形成电容器结构所需的相对较高的第一组热循环不会对浅的P +和N +区域或金属硅化物产生不利影响。在浅区域和金属硅化物的形成期间执行第二组热循环，其与第一组热循环相当或者小于第一组热循环。响应于字线驱动器操作DRAM单元，该字线驱动器被控制以向该字线提供正升压电压和负升压电压，从而控制对DRAM单元的访问。正升压电压大于Vdd但小于Vdd加上晶体管阈值电压Vt的绝对值，类似地，负升压电压小于VSS的量小于Vt。

10. 发明授权

US5729152A Termination circuits for reduced swing signal lines and methods for operating same 失效
标题翻译：用于减少摆动信号线的终端电路及其操作方法
公开(公告)号：US5729152A
公开(公告)日：1998-03-17
申请号：US549610
申请日：1995-10-27
申请人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
发明人： Wingyu Leung , Winston Lee , Fu-Chieh Hsu
IPC分类号： G11C11/41 , G06F3/00 , G06F12/16 , G06F13/16 , G06F13/40 , G11C7/00 , G11C11/401 , G11C11/407 , G11C11/417 , G11C29/00 , G11C29/04 , H04L25/02 , H03K17/16
CPC分类号： H04L25/028 , G06F13/40 , G06F13/4072 , G06F13/4077 , H04L25/026 , H04L25/0292 , Y02B60/1228 , Y02B60/1235
摘要： A memory device which utilizes a plurality of memory modules coupled in parallel to a master I/O module through a single directional asymmetrical signal swing (DASS) bus. This structure provides an I/O scheme having symmetrical swing around half the supply voltage, high through-put, high data bandwidth, short access time, low latency and high noise immunity. The memory device utilizes improved column access circuitry including an improved address sequencing circuit and a data amplifier within each memory module. The memory device includes a resynchronization circuit which allows the device to operate either synchronously and asynchronously using the same pins. Each memory module has independent address and command decoders to enable independent operation. Thus, each memory module is activated by commands on the DASS bus only when a memory access operation is performed within the particular memory module. The memory device includes redundant memory modules to replace defective memory modules. Replacement can be carried out through commands on the DASS bus. The memory device can be configured to simultaneously write a single input data stream to multiple memory modules or to perform high-speed interleaved read and write operations. In one embodiment, multiple memory devices are coupled to a common, high-speed I/O bus without requiring large bus drivers and complex bus receivers in the memory modules.
摘要翻译：一种存储器件，其利用通过单向非对称信号摆幅（DASS）总线并联到主I / O模块的多个存储器模块。这种结构提供了一个在电源电压的一半左右，高输入，高数据带宽，短访问时间，低延迟和高抗噪声的对称摆动的I / O方案。存储器件利用改进的列存取电路，包括改进的地址排序电路和每个存储器模块内的数据放大器。存储器件包括再同步电路，其允许器件使用相同的引脚同步和异步地操作。每个存储器模块具有独立的地址和命令解码器，以实现独立操作。因此，只有当在特定存储器模块内执行存储器访问操作时，每个存储器模块才被DASS总线上的命令激活。存储器件包括用于替换有缺陷的存储器模块的冗余存储器模块。可以通过DASS总线上的命令进行更换。存储器件可被配置为将单个输入数据流同时写入多个存储器模块或执行高速交错读写操作。在一个实施例中，多个存储器件耦合到公共的高速I / O总线，而不需要存储器模块中的大的总线驱动器和复杂的总线接收器。

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