专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20060255850A1 High speed latch circuits using gated diodes 有权
标题翻译：使用门控二极管的高速锁存电路
公开(公告)号：US20060255850A1
公开(公告)日：2006-11-16
申请号：US11491701
申请日：2006-07-24
申请人： Wing Luk , Leland Chang , Robert Dennard , Robert Montoye
发明人： Wing Luk , Leland Chang , Robert Dennard , Robert Montoye
IPC分类号： H03K3/356
CPC分类号： G11C7/065 , G11C7/06 , H03F1/56 , H03F3/10 , H03F3/347 , H03F2200/183
摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.
摘要翻译：读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。

2. 发明申请

US20060050581A1 Sense amplifier circuits and high speed latch circuits using gated diodes 失效
公开(公告)号：US20060050581A1
公开(公告)日：2006-03-09
申请号：US10933706
申请日：2004-09-03
申请人： Wing Luk , Leland Chang , Robert Dennard , Robert Montoye
发明人： Wing Luk , Leland Chang , Robert Dennard , Robert Montoye
IPC分类号： G11C7/00
CPC分类号： G11C7/065 , G11C7/06 , H03F1/56 , H03F3/10 , H03F3/347 , H03F2200/183
摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.

3. 发明申请

US20070164359A1 Area-efficient gated diode structure and method of forming same 有权
标题翻译：区域效能门控二极管结构及其形成方法
公开(公告)号：US20070164359A1
公开(公告)日：2007-07-19
申请号：US11334170
申请日：2006-01-18
申请人： Leland Chang , Robert Dennard , David Fried , Wing Luk
发明人： Leland Chang , Robert Dennard , David Fried , Wing Luk
IPC分类号： H01L27/12
CPC分类号： H01L29/7391 , H01L21/823456 , H01L21/823462 , H01L21/823487
摘要： An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, and at least one trench electrode extending substantially vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is electrically connected to the trench electrode, and at least a second terminal is electrically connected to the active region. The gated diode is operative in one of at least a first mode and a second mode as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer substantially surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being substantially greater than the second capacitance.
摘要翻译：区域有效的门控二极管包括第一导电类型的半导体层，形成在靠近半导体层的上表面的半导体层中的第二导电类型的有源区，以及至少一个沟槽电极，该沟槽电极基本垂直延伸穿过活性层并且至少部分地进入半导体层。门控二极管的第一端子电连接到沟槽电极，并且至少第二端子电连接到有源区域。门控二极管作为施加在第一和第二端子之间的电压电位的函数的至少第一模式和第二模式中的一个工作。第一模式的特征在于在基本上围绕沟槽电极的半导体层中产生反型层。门控二极管具有第一模式中的第一电容和第二模式中的第二电容，第一电容基本上大于第二电容。

4. 发明申请

US20060198181A1 Static random access memory utilizing gated diode technology 有权
标题翻译：采用门控二极管技术的静态随机存取存储器
公开(公告)号：US20060198181A1
公开(公告)日：2006-09-07
申请号：US11067797
申请日：2005-02-28
申请人： Wing Luk , Leland Chang
发明人： Wing Luk , Leland Chang
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A new type of static RAM cell is disclosed that is based on a gated diode and its voltage amplification characteristic. The cell combines the advantages of a static RAM, in which data refresh is not needed, and those of gated diode cells, which are scalable to low voltages, have high signal to noise ratio, high signal margin, and tolerance to process variations, to form a single high performance static memory cell. This new cell has independent read and write paths, which allow for separate optimization of the read (R) and write (W) events, and enable dual-port R/W operation. Furthermore, storage node disturbance during the read and write operations are eliminated, which greatly improves cell stability and scalability for future technologies.
摘要翻译：公开了一种基于门控二极管及其电压放大特性的新型静态RAM单元。该单元结合了不需要数据刷新的静态RAM和可扩展到低电压的门控二极管单元的优点具有高信噪比，高信号余量和对工艺变化的公差，形成单个高性能静态存储单元。这个新单元格具有独立的读写路径，允许单独优化读（R）和写（W）事件，并启用双端口R / W操作。此外，消除了在读取和写入操作期间的存储节点干扰，这大大地改善了用于未来技术的小区稳定性和可扩展性。

5. 发明申请

US20060146638A1 MEMORY CELL HAVING IMPROVED READ STABILITY 有权
标题翻译：具有改进的读取稳定性的存储单元
公开(公告)号：US20060146638A1
公开(公告)日：2006-07-06
申请号：US11069018
申请日：2005-02-28
申请人： Leland Chang , Robert Dennard , Robert Kevin Montoye
发明人： Leland Chang , Robert Dennard , Robert Kevin Montoye
IPC分类号： G11C8/00
CPC分类号： G11C11/413 , H01L27/11 , H01L27/1104
摘要： A memory cell for use in a memory array includes a storage element for storing a logical state of the memory cell, a write circuit and a read circuit. The write circuit is operative to selectively connect a first node of the storage element to at least a first write bit line in the memory array in response to a write signal for selectively writing the logical state of the memory cell. The read circuit includes a substantially high impedance input node connected to the storage element and an output node connectable to a read bit line of the memory array. The read circuit is configured to generate an output signal at the output node which is representative of the logical state of the storage element in response to a read signal applied to the read circuit. The memory cell is configured such that the write circuit is disabled during a read operation of the memory cell so as to substantially isolate the storage element from the first write bit line during the read operation. A strength of at least one transistor device in the storage element is separately optimized relative to a strength of at least one transistor device in the write circuit and/or the read circuit.
摘要翻译：用于存储器阵列的存储单元包括用于存储存储单元的逻辑状态的存储元件，写入电路和读取电路。写入电路用于响应于用于选择性地写入存储器单元的逻辑状态的写入信号，有选择地将存储元件的第一节点连接到存储器阵列中的至少第一写入位线。读取电路包括连接到存储元件的基本上高阻抗的输入节点和可连接到存储器阵列的读取位线的输出节点。读取电路被配置为响应于施加到读取电路的读取信号而在输出节点处产生代表存储元件的逻辑状态的输出信号。存储单元被配置为使得在存储单元的读取操作期间禁止写入电路，以便在读取操作期间基本上将存储元件与第一写入位线隔离。存储元件中的至少一个晶体管器件的强度相对于写入电路和/或读取电路中的至少一个晶体管器件的强度分别优化。

6. 发明授权

US07116594B2 Sense amplifier circuits and high speed latch circuits using gated diodes 失效
标题翻译：感应放大器电路和使用门控二极管的高速锁存电路
公开(公告)号：US07116594B2
公开(公告)日：2006-10-03
申请号：US10933706
申请日：2004-09-03
申请人： Wing K. Luk , Leland Chang , Robert H. Dennard , Robert Montoye
发明人： Wing K. Luk , Leland Chang , Robert H. Dennard , Robert Montoye
IPC分类号： G11C7/00 , G11C7/02 , G01R19/00 , H03F3/60
CPC分类号： G11C7/065 , G11C7/06 , H03F1/56 , H03F3/10 , H03F3/347 , H03F2200/183
摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.
摘要翻译：读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。

7. 发明授权

US07242629B2 High speed latch circuits using gated diodes 有权
标题翻译：使用门控二极管的高速锁存电路
公开(公告)号：US07242629B2
公开(公告)日：2007-07-10
申请号：US11491701
申请日：2006-07-24
申请人： Wing K. Luk , Leland Chang , Robert H. Dennard , Robert Montoye
发明人： Wing K. Luk , Leland Chang , Robert H. Dennard , Robert Montoye
IPC分类号： G11C7/00 , G11C7/02 , G01R19/00 , H03F3/60
CPC分类号： G11C7/065 , G11C7/06 , H03F1/56 , H03F3/10 , H03F3/347 , H03F2200/183
摘要： A sense amplifier circuit comprises (1) an isolation device comprising a control terminal and first and second terminals, the first terminal of the isolation device coupled to a signal line, (2) a gated diode comprising first and second terminals, the first terminal of the gated diode coupled to the second terminal of the isolation device, and the second terminal of the gated diode coupled to a set line; and (3) control circuitry coupled to the control terminal of the isolation device and adapted to control voltage on the control terminal of the isolation device in order to enable and disable the isolation device. A latch circuit further comprises a precharge device comprising a control terminal and first and second terminals, the first terminal of the precharge device coupled to a power supply voltage, and the second terminal of the precharge device coupled to the first terminal of the isolation device.
摘要翻译：读出放大器电路包括（1）隔离装置，其包括控制端子和第一和第二端子，隔离装置的第一端子耦合到信号线，（2）门控二极管，包括第一和第二端子，第一端子所述门控二极管耦合到隔离装置的第二端子，并且门控二极管的第二端子耦合到设定线路; 和（3）耦合到隔离装置的控制端子并且适于控制隔离装置的控制端子上的电压的控制电路，以便启用和禁用隔离装置。闩锁电路还包括预充电装置，其包括控制端子和第一和第二端子，预充电装置的第一端子耦合到电源电压，并且预充电装置的第二端子耦合到隔离装置的第一端子。

8. 发明授权

US09118242B2 Slab inductor device providing efficient on-chip supply voltage conversion and regulation 有权
标题翻译：板式电感器件提供有效的片上电源电压转换和调节
公开(公告)号：US09118242B2
公开(公告)日：2015-08-25
申请号：US13595016
申请日：2012-08-27
申请人： Leland Chang , David Goren , Naigang Wang
发明人： Leland Chang , David Goren , Naigang Wang
IPC分类号： G06F1/26 , H02M3/155 , H02M3/156
CPC分类号： H02M3/158 , G06F1/26 , H02M3/155 , H02M3/156
摘要： A method is disclosed to operate a voltage conversion circuit such as a buck regulator circuit that has a plurality of switches coupled to a voltage source; a slab inductor having a length, a width and a thickness, where the slab inductor is coupled between the plurality of switches and a load and carries a load current during operation of the plurality of switches; and a means to reduce or cancel the detrimental effect of other wires on same chip, such as a power grid, potentially conducting return current and thereby degrading the functionality of this slab inductor. In one embodiment the wires can be moved further away from the slab inductor and in another embodiment magnetic materials can be used to shield the slab inductor from at least one such interfering conductor.
摘要翻译：公开了一种用于操作诸如降压调节器电路的电压转换电路的方法，该电压转换电路具有耦合到电压源的多个开关; 具有长度，宽度和厚度的平板电感器，其中所述平板电感器耦合在所述多个开关之间，并且在所述多个开关的操作期间负载并承载负载电流; 以及减少或消除其他电线对同一芯片（例如电力网）的有害影响的手段，可能导致返回电流，从而降低该板式电感器的功能。在一个实施例中，电线可以进一步远离板式电感器，并且在另一个实施例中，磁性材料可用于屏蔽平板电感器与至少一个这样的干扰导体。

9. 发明授权

US08828800B2 Method of forming adaptive interconnect structure having programmable contacts 有权
标题翻译：形成具有可编程触点的自适应互连结构的方法
公开(公告)号：US08828800B2
公开(公告)日：2014-09-09
申请号：US13417444
申请日：2012-03-12
申请人： Leland Chang , Matthew R. Wordeman , Albert M. Young
发明人： Leland Chang , Matthew R. Wordeman , Albert M. Young
IPC分类号： H01L23/525
CPC分类号： H01L25/0657 , H01L23/5252 , H01L23/5256 , H01L24/06 , H01L24/14 , H01L24/16 , H01L25/50 , H01L2224/0401 , H01L2224/05555 , H01L2224/05624 , H01L2224/05647 , H01L2224/05684 , H01L2224/13099 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01074 , H01L2924/014 , H01L2924/04953 , H01L2924/00014
摘要： An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.
摘要翻译：半导体结构上的接触焊盘阵列的间距小于用于垂直堆叠半导体结构的接合工艺的覆盖公差的两倍。用于匹配接触针的覆盖变化区域内的一组接触焊盘可以电连接到可编程触点阵列，使得一个可编程触点连接到覆盖变化区域内的每个接触焊盘。一个接触垫可以设置有多个可编程触点。在半导体结构堆叠之后，通过连接或断开可编程触点来容纳接触引脚和接触焊盘之间的接触的可变性。由于接触引脚阵列的间距可能小于接合过程的覆盖变化的两倍，所以垂直堆叠结构中提供了高密度的互连。

10. 发明授权

US08687398B2 Sense scheme for phase change material content addressable memory 有权
标题翻译：相变材料内容可寻址存储器的感应方案
公开(公告)号：US08687398B2
公开(公告)日：2014-04-01
申请号：US13407813
申请日：2012-02-29
申请人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
发明人： Leland Chang , Chung H. Lam , Jing Li , Robert K. Montoye
IPC分类号： G11C15/00
CPC分类号： G11C15/00
摘要： A sensing circuit and method for sensing match lines in content addressable memory. The sensing circuit includes an inverter electrically coupled in a feedback loop to a match line. The inverter includes an inverting threshold of the match line. The match line is charged to substantially a first voltage threshold during a pre-charge phase. An evaluation phase occurs when the match line voltage drops from substantially the first voltage threshold to substantially the second voltage threshold.
摘要翻译：一种用于感测内容可寻址存储器中匹配线的感测电路和方法。感测电路包括电反馈回路中电耦合到匹配线的反相器。逆变器包括匹配线的反相阈值。在预充电阶段期间，将匹配线充电至基本上第一电压阈值。当匹配线电压从基本上从第一电压阈值下降到基本上第二电压阈值时，发生评估阶段。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式