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    • 1. 发明申请
    • Systems and methods for flexible extension of SAS expander ports
    • SAS扩展端口灵活扩展的系统和方法
    • US20050193178A1
    • 2005-09-01
    • US10788590
    • 2004-02-27
    • William VoorheesCarl Gygi
    • William VoorheesCarl Gygi
    • G06F12/00G06F13/38
    • G06F13/385
    • A multi-chip module (MCM) designed using standard die SAS expander components for rapidly designing a customized SAS expander having a predetermined number of ports. A number of standard expander die circuit components are selected and disposed on a MCM design. Each expander die circuit has a predetermined number of internal ports within the MCM and a predetermined number of ports for coupling to SAS devices external to the MCM. An internal fabric is disposed on the MCM and selectively coupled to internal ports of the SAS expanders to provide the desired number of external ports with desired routing therebetween. The internal fabric may be statically configured or dynamically programmed. The internal fabric routing may provide wide port routes as well as standard port connections.
    • 使用标准模块SAS扩展器组件设计的多芯片模块(MCM),用于快速设计具有预定数量端口的定制SAS扩展器。 多个标准扩展器裸片电路组件被选择和布置在MCM设计上。 每个扩展器管芯电路具有MCM内的预定数量的内部端口和用于耦合到MCM外部的SAS设备的预定数量的端口。 内部结构布置在MCM上并选择性地耦合到SAS扩展器的内部端口,以提供期望数量的外部端口,其间具有期望的布线。 内部结构可以静态配置或动态编程。 内部结构路由可以提供宽端口路由以及标准端口连接。
    • 4. 发明申请
    • APPARATUS AND METHODS FOR IMPROVED HIGH-SPEED COMMUNICATION SYSTEMS
    • 改进的高速通信系统的装置和方法
    • US20110103439A1
    • 2011-05-05
    • US12613416
    • 2009-11-05
    • Luke E. McKayCarl GygiBrian K. EinsweilerBrian J. Varney
    • Luke E. McKayCarl GygiBrian K. EinsweilerBrian J. Varney
    • H04B1/38
    • H04L25/0292H04L5/1423H04L25/08H04L25/14
    • Apparatus and methods for improved high-speed communication by exchanging low-speed information regarding the high-speed exchanges over the same communication medium. In one exemplary embodiment, a communication device includes a high-speed transceiver adapted to exchange high-speed data with another device via a communication medium using high-frequency signals. The device also includes a low-speed component adapted to exchange low-speed information over the same communication medium as low-frequency signals. The low-frequency signals may be applied as common mode signals to a differential communication path so as to not interfere with the high-speed data exchanges. In another embodiment, a high-pass filter may be included in the device to remove the low-frequency signals before the high-speed data is applied to the high-speed transceiver. Responsive to receipt of the low-speed information, a device may adjust parameters of the transceiver to improve the high-speed data exchanges.
    • 通过在相同的通信介质上交换关于高速交换的低速信息来改进高速通信的装置和方法。 在一个示例性实施例中,通信设备包括适于经由使用高频信号的通信介质与另一设备交换高速数据的高速收发器。 该装置还包括适于在与低频信号相同的通信介质上交换低速信息的低速分量。 低频信号可以作为共模信号施加到差分通信路径,以便不干扰高速数据交换。 在另一个实施例中,在将高速数据应用于高速收发器之前,高通滤波器可以包括在该装置中以去除低频信号。 响应于接收低速信息,设备可以调整收发器的参数,以改善高速数据交换。
    • 5. 发明授权
    • Methods and apparatus for burst data transfers between double data rate (DDR) memories and embedded processors during training
    • 训练期间双数据速率(DDR)存储器和嵌入式处理器之间的突发数据传输的方法和装置
    • US08606989B2
    • 2013-12-10
    • US12872731
    • 2010-08-31
    • Craig R. ChafinCarl GygiAdam S. Browen
    • Craig R. ChafinCarl GygiAdam S. Browen
    • G06F12/00G06F1/04
    • G06F12/0879G06F12/1027
    • Methods and apparatus are provided for burst transfers of data between DDR memories and embedded processors during training of the PHY interface in an embedded system. An embedded system comprises an embedded processor having at least one cache controller; a memory, wherein the memory has an atomic memory access that comprises a plurality of clock edges; and a memory controller having a physical interface to convert digital signals between the embedded processor and the memory, wherein the cache controller executes a training process to determine a delay through the physical interface for each of the plurality of clock edges using a burst transfer of data. The burst transfer comprises reading a data pattern from the memory and storing the data pattern in one or more registers in the embedded processor.
    • 提供了用于在嵌入式系统中的PHY接口的训练期间在DDR存储器和嵌入式处理器之间的数据突发传输的方法和装置。 嵌入式系统包括具有至少一个高速缓存控制器的嵌入式处理器; 存储器,其中所述存储器具有包括多个时钟边缘的原子存储器访问; 以及存储器控制器,具有物理接口以在所述嵌入式处理器和所述存储器之间转换数字信号,其中所述高速缓存控制器执行训练处理,以使用数据的突发传送来确定所述多个时钟边缘中的每一个的物理接口的延迟 。 突发传送包括从存储器读取数据模式并将数据模式存储在嵌入式处理器中的一个或多个寄存器中。
    • 8. 发明申请
    • METHODS AND STRUCTURE FOR ANALYZING DIFFERENT SIGNALING PATHWAYS THROUGH A TEST SIGNAL SELECTION HIERARCHY
    • 通过测试信号选择分析不同信号通路的方法和结构
    • US20140052404A1
    • 2014-02-20
    • US13586048
    • 2012-08-15
    • Coralyn S. GauvinSteven E. StartCarl Gygi
    • Coralyn S. GauvinSteven E. StartCarl Gygi
    • G06F19/00
    • G01R31/31708G01R31/31725
    • Methods and structure are disclosed for analyzing different signaling pathways through a test signal selection hierarchy utilizing test patterns. One embodiment comprises an integrated circuit that includes a block of circuitry, a test signal generator, and a test signal selection hierarchy. The block of circuitry generates internal operational (TOP) signals for performing functions. The test signal generator generates test patterns that correspond with the IOP signals. The test signal selection hierarchy receives IOP signals and the test patterns, and selectively routes received signals to test pads. The test signal selection hierarchy routes the test patterns via signaling pathways through the test signal selection hierarchy to provide outputs signals on the test pads. The output signals are usable by an external test system to determine two or more of: a crosstalk, inter-symbol interference, a signal skew, and a threshold voltage for detecting bit transition on signaling pathways.
    • 公开了用于通过使用测试图案的测试信号选择层级来分析不同信号通路的方法和结构。 一个实施例包括集成电路,其包括电路块,测试信号发生器和测试信号选择层级。 电路块产生用于执行功能的内部操作(TOP)信号。 测试信号发生器产生与IOP信号相对应的测试图形。 测试信号选择层级接收IOP信号和测试图案,并且将接收到的信号选择性地路由到测试焊盘。 测试信号选择层级通过信号通路将测试模式通过测试信号选择层次结构,以在测试焊盘上提供输出信号。 输出信号可由外部测试系统使用,以确定以下两个或多个:串扰,符号间干扰,信号偏移和阈值电压,用于检测信号通路上的位转换。
    • 10. 发明授权
    • Apparatus and methods for improved high-speed communication systems
    • 用于改进高速通信系统的装置和方法
    • US08331429B2
    • 2012-12-11
    • US12613416
    • 2009-11-05
    • Luke E. McKayCarl GygiBrian K. EinsweilerBrian J. Varney
    • Luke E. McKayCarl GygiBrian K. EinsweilerBrian J. Varney
    • H04B1/38H04L5/16
    • H04L25/0292H04L5/1423H04L25/08H04L25/14
    • Apparatus and methods for improved high-speed communication by exchanging low-speed information regarding the high-speed exchanges over the same communication medium. In one exemplary embodiment, a communication device includes a high-speed transceiver adapted to exchange high-speed data with another device via a communication medium using high-frequency signals. The device also includes a low-speed component adapted to exchange low-speed information over the same communication medium as low-frequency signals. The low-frequency signals may be applied as common mode signals to a differential communication path so as to not interfere with the high-speed data exchanges. In another embodiment, a high-pass filter may be included in the device to remove the low-frequency signals before the high-speed data is applied to the high-speed transceiver. Responsive to receipt of the low-speed information, a device may adjust parameters of the transceiver to improve the high-speed data exchanges.
    • 通过在相同的通信介质上交换关于高速交换的低速信息来改进高速通信的装置和方法。 在一个示例性实施例中,通信设备包括适于经由使用高频信号的通信介质与另一设备交换高速数据的高速收发器。 该装置还包括适于在与低频信号相同的通信介质上交换低速信息的低速分量。 低频信号可以作为共模信号施加到差分通信路径,以便不干扰高速数据交换。 在另一个实施例中,在将高速数据应用于高速收发器之前,高通滤波器可以包括在该装置中以去除低频信号。 响应于接收低速信息,设备可以调整收发器的参数,以改善高速数据交换。