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1. 发明授权

US4245299A System providing adaptive response in information requesting unit 失效
标题翻译：在信息请求单元中提供自适应响应的系统
公开(公告)号：US4245299A
公开(公告)日：1981-01-13
申请号：US867262
申请日：1978-01-05
申请人： William E. Woods , Richard A. Lemay , John L. Curley
发明人： William E. Woods , Richard A. Lemay , John L. Curley
IPC分类号： G06F13/38 , G06F13/16 , G06F13/378 , G06F13/42 , G06F3/04 , G08C15/00
CPC分类号： G06F13/378 , G06F13/4213
摘要： In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a first unit, such as a central processor, to make a multiple fetch request of a second unit, such as a memory, during a first transfer cycle. The multiple fetch request requests the second unit to transfer multiple parts of data to the first unit during multiple further transfer cycles, wherein one part of data is transferred in each further transfer cycle. Logic is provided in the second unit to enable the second unit to indicate to the first unit, except during the last further transfer cycle, that each further transfer cycle will be followed by another further transfer cycle. Logic is provided in the first unit to enable the first unit to accept less parts of data than originally requested in the multiple fetch request. This permits the first unit to make multiple fetch requests of other units on the bus without regard to whether the other units are capable of performing multiple fetch operations and eliminates the need for abnormal condition recovery logic in the second unit. Logic is also provided to permit the first unit to utilize each part of data as it is received by the first unit without requiring the first unit to wait for the last transfer cycle before using any of the received parts of data.
摘要翻译：在包括诸如数据处理系统之类的多个单元连接的公共总线的系统中，在异步生成的总线传送周期期间，信息可以由最高优先级单元传送。逻辑被提供用于使第一单元（例如中央处理器）能够在第一传送周期期间进行诸如存储器的第二单元的多次提取请求。多次提取请求请求第二单元在多个其它传送周期期间将多个数据部分传送到第一单元，其中在每个进一步的传送周期中传送一部分数据。在第二单元中提供逻辑以使第二单元能够向第一单元指示，除了在最后一个进一步的传送周期内，每个进一步的传送周期将跟随另一传送周期。在第一单元中提供逻辑以使得第一单元能够接收比原来在多次提取请求中要求的更少的数据部分。这允许第一单元在总线上进行其他单元的多个提取请求，而不考虑其他单元是否能够执行多次获取操作，并且不需要第二单元中的异常状态恢复逻辑。还提供逻辑以允许第一单元利用第一单元接收的数据的每个部分，而不需要第一单元在使用任何接收的数据部分之前等待最后的传送周期。

2. 发明授权

US4727486A Hardware demand fetch cycle system interface 失效
标题翻译：硬件需求提取循环系统界面
公开(公告)号：US4727486A
公开(公告)日：1988-02-23
申请号：US858786
申请日：1986-05-02
申请人： Michael D. Smith , Llewelyn S. Dunwell , Richard A. Lemay , Robert C. Miller , Theodore R. Staplin, Jr. , William E. Woods , John L. Curley
发明人： Michael D. Smith , Llewelyn S. Dunwell , Richard A. Lemay , Robert C. Miller , Theodore R. Staplin, Jr. , William E. Woods , John L. Curley
IPC分类号： G06F12/10 , G06F9/00 , G06F9/22 , G06F9/30
CPC分类号： G06F12/1054
摘要： A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.

3. 发明授权

US4181974A System providing multiple outstanding information requests 失效
标题翻译：系统提供多个未完成的信息请求
公开(公告)号：US4181974A
公开(公告)日：1980-01-01
申请号：US867266
申请日：1978-01-05
申请人： Richard A. Lemay , John L. Curley
发明人： Richard A. Lemay , John L. Curley
IPC分类号： G06F13/37 , G06F13/16 , G06F13/368 , G06F13/42 , G06F3/00 , G06F1/04
CPC分类号： G06F13/368 , G06F13/4213
摘要： In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred during asynchronously generated information transfer cycles. Logic is provided for enabling a first unit to transfer first information to a second unit during a first request transfer cycle requesting that the second unit transfer second information to the first unit during a later first response transfer cycle. Logic is also provided to enable the first unit to transfer third information to a third unit during a second request transfer cycle requesting that the third unit transfer fourth information to the first unit during a later second response transfer cycle. Logic is provided that enable the first unit to transfer the third information before receiving the second information and logic is further provided that enables the first unit to receive the second information before or after receiving the fourth information. Logic is provided for enabling any other unit to communicate over the common bus during the time between the first request transfer cycle and the latest transfer cycle associated with the transfer of the second and fourth information.
摘要翻译：在包括公共总线的系统中，诸如数据处理系统之类的多个单元被连接用于信息传送的公共总线，可以在异步生成的信息传送周期期间传送信息。逻辑被提供用于使得第一单元能够在第一请求传送周期期间将第一信息传送到第二单元，请求第二单元在稍后的第一响应传送周期期间将第二信息传送到第一单元。还提供逻辑以使得第一单元能够在第二请求传送周期期间将第三信息传送到第三单元，请求第三单元在稍后的第二响应传送周期期间将第四信息传送到第一单元。提供逻辑，使得第一单元能够在接收第二信息之前传送第三信息，并且进一步提供使第一单元能够在接收第四信息之前或之后接收第二信息的逻辑。逻辑被提供用于使得任何其他单元能够在第一请求传送周期与与第二和第四信息的传送相关联的最新传送周期之间的时间内通过公共总线进行通信。

4. 发明授权

US4236203A System providing multiple fetch bus cycle operation 失效
标题翻译：系统提供多个提取总线循环操作
公开(公告)号：US4236203A
公开(公告)日：1980-11-25
申请号：US867270
申请日：1978-01-05
申请人： John L. Curley , Robert B. Johnson , Richard A. Lemay , Chester M. Nibby, Jr.
发明人： John L. Curley , Robert B. Johnson , Richard A. Lemay , Chester M. Nibby, Jr.
IPC分类号： G06F13/00 , G06F13/16 , G06F13/368 , G06F13/37 , G06F13/42 , G06F1/04
CPC分类号： G06F13/368 , G06F13/4213
摘要： In a system which includes a common bus to which a plurality of units are connected for the transfer of information, such as a data processing system, information may be transferred by the highest priority requesting unit during an asynchronously generated bus transfer cycle. Logic is provided for enabling a multiple fetch operation in which the master unit requesting multiple words of information from the slave unit during a first bus transfer cycle may receive such information from the slave unit during a series of later slave generated bus cycles. Logic is provided for enabling any other units to communicate over the common bus during the time between the first cycle and such last cycle during which the slave unit responds, thereby enabling at least two pairs of units to communicate with each other respectively, in an interleaved manner.
摘要翻译：在包括公共总线的系统中，诸如数据处理系统的用于传送信息的多个单元连接到该公共总线，在异步生成的总线传送周期期间，信息可以由最高优先级请求单元传送。逻辑被提供用于实现多次提取操作，其中主单元在第一总线传送周期期间从从单元请求多个信息字可以在一系列随后从站产生的总线周期期间从从单元接收这些信息。逻辑被提供用于使得任何其他单元能够在第一周期与从单元响应的最后周期之间的时间内通过公共总线进行通信，从而使得至少两对单元能够分别在交织的方式。

5. 发明授权

US4464717A Multilevel cache system with graceful degradation capability 失效
标题翻译：多级缓存系统具有优雅的降级能力
公开(公告)号：US4464717A
公开(公告)日：1984-08-07
申请号：US364052
申请日：1982-03-31
申请人： James W. Keeley , Edwin P. Fisher , John L. Curley
发明人： James W. Keeley , Edwin P. Fisher , John L. Curley
IPC分类号： G06F12/08 , G06F12/12 , G11C29/00 , G06F13/00
CPC分类号： G11C29/88 , G06F12/126 , G06F2212/1032
摘要： The directory and cache store of a multilevel set associative cache system are organized in levels of memory locations. Round robin replacement apparatus is used to identify in which one of the multilevels information is to be replaced. The directory includes parity detection apparatus for detecting errors in the addresses being written in the directory during a cache memory cycle of operation. Control apparatus combines such parity errors with signals indicative of directory hits to produce invalid hit detection signals. The control apparatus in response to the occurrence of a first invalid hit detection signal conditions the round robin apparatus as well as other portions of the cache system to limit cache operation to those sections whose levels are error free thereby gracefully degrading cache operation.
摘要翻译：多级组关联高速缓存系统的目录和缓存存储器以存储器位置的级别组织。循环替换装置用于识别要更换哪一个多级别信息。该目录包括用于在高速缓冲存储器操作循环期间检测写入目录中的地址中的错误的奇偶校验检测装置。控制装置将这种奇偶校验错误与指示目录命中的信号组合以产生无效命中检测信号。响应于第一无效命中检测信号的发生，控制装置对循环装置以及高速缓存系统的其他部分进行调节，以将高速缓存操作限制在那些级别无错误的部分，从而正确地降低缓存操作。

6. 发明授权

US5721876A Sockets application program mechanism for proprietary based application programs running in an emulation environment 失效
标题翻译：用于在仿真环境中运行的基于专有的应用程序的套接字应用程序机制
公开(公告)号：US5721876A
公开(公告)日：1998-02-24
申请号：US413333
申请日：1995-03-30
申请人： Kin C. Yu , John L. Curley
发明人： Kin C. Yu , John L. Curley
IPC分类号： G06F9/455 , G06F9/46 , G06F3/00 , G06F15/63
CPC分类号： G06F9/544 , G06F9/45537
摘要： A host data processing system operating under the control of a host operating system such as an enhanced version of the UNIX operating system on a RISC based hardware platform includes an emulator which runs as an application process for executing emulated system (ES) user application programs. The emulator includes a number of emulated system executive service components including a socket command handler unit and a socket library component operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server components operating in host memory. The host operating system further includes a host socket library interface layer (API) which operatively connects through a TCP/IP network protocol stack to the communications facilities of the hardware platform. The socket server components operatively connect ES TCP/IP application programs to the socket library interface layer of the host operating system when such application programs issue standard ES socket library calls. The socket command handler unit maps the ES socket library calls into appropriate input/output requests directed to the EMCU. The EMCU directs the requests to an appropriate socket server component which in turn issues the appropriate host socket library calls to the host socket interface layer thereby eliminating both the need to communicate through additional protocol stacks and to provide additional communication hardware facilities.
摘要翻译：在诸如基于RISC的硬件平台上的UNIX操作系统的增强版本的主机操作系统的控制下操作的主机数据处理系统包括作为用于执行仿真系统（ES）用户应用程序的应用程序进程的仿真器。仿真器包括许多仿真的系统执行服务组件，包括套接字命令处理器单元和在共享存储器中操作的套接字库组件，解释器，仿真器监视器调用单元（EMCU）以及在主机存储器中操作的多个服务器组件。主机操作系统还包括主机套接字库接口层（API），其通过TCP / IP网络协议栈可操作地连接到硬件平台的通信设施。当这种应用程序发出标准ES套接字库调用时，套接字服务器组件可操作地将ES TCP / IP应用程序连接到主机操作系统的套接字库接口层。套接字命令处理器单元将ES套接字库调用映射到指向EMCU的适当输入/输出请求。 EMCU将请求引导到适当的套接字服务器组件，该套件服务器组件又向主机套接字层发送适当的主机套接字库调用，从而消除了通过附加协议栈进行通信的需要，并提供额外的通信硬件设施。

7. 发明授权

US5675771A Mechanism for enabling emulation system users to directly invoke a number of host system facilities for executing host procedures either synchronously or asynchronously in a secure manner through automatically created shell mechanisms 失效
标题翻译：使仿真系统用户能够通过自动创建的外壳机制以安全的方式直接调用多个主机系统设备来同步或异步地执行主机过程的机制
公开(公告)号：US5675771A
公开(公告)日：1997-10-07
申请号：US311649
申请日：1994-09-23
申请人： John L. Curley , Thomas S. Hirsch , James W. Stonier , Kin C. Yu
发明人： John L. Curley , Thomas S. Hirsch , James W. Stonier , Kin C. Yu
IPC分类号： G06F1/00 , G06F9/455 , G06F9/46 , G06F13/10 , G06F21/00 , G06F15/16
CPC分类号： G06F13/10 , G06F13/105 , G06F21/31 , G06F21/6281 , G06F9/45537 , G06F2221/2105
摘要： A host data processing system which includes a plurality of input/output devices operates under the control of an enhanced version of the UNIX operating system. The host system includes an emulator which runs as an application process for executing user emulated system (ES) application programs. The emulator includes a number of emulated system executive service components operating in shared memory and an interpreter, an emulator monitor call unit (EMCU) and a number of server facilities operating in the host memory. The ES executive service command handler component is extended to accommodate a number of dual decor commands which invoke host system facilities to execute terminal based commands either synchronously or asynchronously through the automatic creation of host shell mechanisms directly accessible by emulated system users. The server facilities include a network terminal driver (NTD) server for executing emulated system user terminal requests through host system drivers. Additionally, the NTD server includes mechanisms enabling a user to have direct terminal access to host facilities for executing procedures through such shell mechanisms. The mechanisms perform trusted user level validation when each dual decor command is issued and the shell mechanisms use the host access control mechanisms for checking access when the procedure is executed preventing both unauthorized user access and compromises in user data through the improper use of dual decor commands.
摘要翻译：包括多个输入/输出设备的主机数据处理系统在UNIX操作系统的增强版本的控制下操作。主机系统包括作为执行用户仿真系统（ES）应用程序的应用程序运行的仿真器。仿真器包括在共享存储器中操作的多个模拟系统执行服务组件和解释器，仿真器监视器呼叫单元（EMCU）以及在主机存储器中操作的多个服务器设备。 ES执行服务命令处理程序组件被扩展以适应一些双重装饰命令，其通过自动创建由仿真系统用户直接访问的主机壳机制来同步或异步地调用主机系统设施来执行基于终端的命令。服务器设备包括用于通过主机系统驱动程序执行仿真系统用户终端请求的网络终端驱动器（NTD）服务器。此外，NTD服务器包括使得用户能够直接终端访问主机设施以执行通过这些机壳的过程的机制。当执行每个双重装饰命令时，这些机制执行受信任的用户级别验证，并且当执行该过程时，shell机制使用主机访问控制机制来检查访问，以防止未经授权的用户访问并且通过不正确地使用双装饰命令来损害用户数据。

8. 发明授权

US5027271A Apparatus and method for alterable resource partitioning enforcement in a data processing system having central processing units using different operating systems 失效
标题翻译：在具有使用不同操作系统的中央处理单元的数据处理系统中可更改资源划分实施的装置和方法
公开(公告)号：US5027271A
公开(公告)日：1991-06-25
申请号：US136056
申请日：1987-12-21
申请人： John L. Curley , Thomas S. Hirsch , David A. Wurz
发明人： John L. Curley , Thomas S. Hirsch , David A. Wurz
IPC分类号： G06F9/48 , G06F9/50 , G06F15/16 , G06F15/167 , G06F15/177
CPC分类号： G06F9/4843 , G06F15/161 , G06F9/468 , G06F9/5061
摘要： In a data processing system having a plurality of non-homogeneous central processing units, apparatus is disclosed that permits a central processing unit not having mechanisms for protection of the allocation of resources to be coupled to the data processing system while preserving a peer relationship among the central processing units. The protection apparatus is interposed between the coupled central processing unit and the system bus and reviews each access to data processing system resources to insure that the accessed system resource is available to the associated data processing system. In addition, the apparatus permits initialization procedures without interprocessor conflict, provides status information from the coupled central processing unit to a requesting central processing unit and permits selected control signals to be applied to the coupled central processing unit.

9. 发明授权

US5230065A Apparatus and method for a data processing system having a peer relationship among a plurality of central processing units 失效
标题翻译：一种在多个中央处理单元之间具有对等关系的数据处理系统的装置和方法
公开(公告)号：US5230065A
公开(公告)日：1993-07-20
申请号：US544058
申请日：1990-06-25
申请人： John L. Curley , Thomas S. Hirsch , John C. Penney , Ileana S. Reisch , Theodore R. Staplin, Jr. , David A. Wurz
发明人： John L. Curley , Thomas S. Hirsch , John C. Penney , Ileana S. Reisch , Theodore R. Staplin, Jr. , David A. Wurz
IPC分类号： G06F9/48 , G06F9/50 , G06F13/38 , G06F15/16
CPC分类号： G06F9/4843 , G06F13/387 , G06F15/161 , G06F9/5011
摘要： A data processing system is disclosed in which a plurality of central processing units have access to all the system resources, i.e., have a peer relationship. During initialization of the data processing system, all the system resources are allocated to the individual central processing units according to a preselected distribution procedure, the identification of available resources thereafter being stored in the files of the individual central processing units. During the operation of the data processing system, the resources can be reallocated by a predetermined procedure. The central processing units entering such a relationship are required to include apparatus and/or software procedures that prevent access to system resources not assigned thereto. A mail box procedure, using locations in the main memory unit permit communication between the central processing units and are used in the dynamic allocation of resources.
摘要翻译：公开了一种数据处理系统，其中多个中央处理单元可以访问所有系统资源，即具有对等关系。在数据处理系统的初始化期间，根据预先选择的分配过程将所有系统资源分配给各个中央处理单元，然后将可用资源的识别存储在各个中央处理单元的文件中。在数据处理系统的操作期间，可以通过预定的过程重新分配资源。输入这种关系的中央处理单元需要包括防止访问未分配给它的系统资源的装置和/或软件程序。使用主存储器单元中的位置的邮箱过程允许中央处理单元之间的通信，并且用于动态分配资源。

10. 发明授权

US4827400A Segment descriptor present bit recycle and detect logic for a memory management unit 失效
标题翻译：段描述符提供存储器管理单元的位回收和检测逻辑
公开(公告)号：US4827400A
公开(公告)日：1989-05-02
申请号：US848513
申请日：1986-04-07
申请人： Llewelyn S. Dunwell , Richard P. Brown , Arthur Peters , John L. Curley
发明人： Llewelyn S. Dunwell , Richard P. Brown , Arthur Peters , John L. Curley
IPC分类号： G06F12/02 , G06F12/08
CPC分类号： G06F12/0292
摘要： A data processing system includes a logical address to a physical address translator in an extended memory management unit. A 128 word memory stores task segment descriptor words which include a base address. A 16 word memory stores corresponding present bits to indicate if the addressed task segment descriptor is present in its memory. This arrangement allows a 128 word memory to be cleared in 16 memory cycles.
摘要翻译：数据处理系统包括到扩展存储器管理单元中的物理地址转换器的逻辑地址。 128字存储器存储包括基地址的任务段描述符字。 16字存储器存储对应的当前位以指示所寻址的任务段描述符是否存在于其存储器中。这种布置允许在16个存储器周期中清除128个字存储器。

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