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1. 发明授权

US6055268A Multimode digital modem 失效
标题翻译：多模数字调制解调器
公开(公告)号：US6055268A
公开(公告)日：2000-04-25
申请号：US667267
申请日：1996-06-20
申请人： William C. Timm , Walter Y. Chen , Gene A. Frantz , Domingo G. Garcia , Xiaolin Lu , Dennis G. Mannering , Michael O. Polley , Terence J. Riley , Donald P. Shaver , Song Wu , Alan Gatherer , Paul E. Schurr , Douglas B. Weiner
发明人： William C. Timm , Walter Y. Chen , Gene A. Frantz , Domingo G. Garcia , Xiaolin Lu , Dennis G. Mannering , Michael O. Polley , Terence J. Riley , Donald P. Shaver , Song Wu , Alan Gatherer , Paul E. Schurr , Douglas B. Weiner
IPC分类号： H04L29/10 , H04J11/00 , H04L1/00 , H04L1/16 , H04L5/14 , H04L25/03 , H04L25/49 , H04L27/26 , H04M11/00 , H04M11/06 , H03H7/30 , H03H7/40 , H03K5/159
CPC分类号： H04L1/0023 , H04L1/0003 , H04L1/0009 , H04L1/0016 , H04L25/03 , H04L25/03343 , H04L25/4921 , H04L27/2647 , H04L27/2649 , H04L27/2675 , H04L5/1438 , H04M11/06 , H04M11/062 , H04L1/0059 , H04L1/16 , H04L2025/03414 , H04L2025/03611 , Y02B60/31 , Y02B60/36
摘要： A modem communication system with receiving and transmission paths includes a direct equalizer system having an adaptive filter (1532) in the transmission path to compensate for frequency distortion of the communication channel. The transmitter filter coefficients are adapted by a filter coefficient calculator (1528), under control of a data detector (1526) which detects incoming data in the receiving path. A switch (1534) is controlled by status of a transmit output data buffer to multiplex either the training sequence or output data into the transmission path. When the buffer is idle, the training sequence generator (1540) is linked to a digital-to-analog (D/A) converter (1536) and line driver (1538). The receiving path includes an isolation switch (1520), a receiver amplifier (1522) and a slicer (1524). The receiver correlates the received training sequence with a known training sequence and updates the equalizer filter coefficients using an adaptation algorithm, such as a least mean squared algorithm. A first embodiment utilizes a high speed digital programmable filter (1532). Another embodiment utilizes a data buffer (1533) which is periodically filled with data filtered by a digital signal processor (DSP).
摘要翻译：具有接收和传输路径的调制解调器通信系统包括在传输路径中具有自适应滤波器（1532）的直接均衡器系统，以补偿通信信道的频率失真。在由检测接收路径中的输入数据的数据检测器（1526）的控制下，发射机滤波器系数由滤波器系数计算器（1528）适配。开关（1534）由发送输出数据缓冲器的状态控制，以将训练序列或输出数据复用到传输路径中。当缓冲器空闲时，训练序列发生器（1540）链接到数模（D / A）转换器（1536）和线驱动器（1538）。接收路径包括隔离开关（1520），接收放大器（1522）和限幅器（1524）。接收器将接收到的训练序列与已知的训练序列进行相关，并使用诸如最小均方算法的自适应算法来更新均衡器滤波器系数。第一实施例利用高速数字可编程滤波器（1532）。另一个实施例利用周期性地填充由数字信号处理器（DSP）滤波的数据的数据缓冲器（1533）。

2. 发明授权

US06732224B2 System with control data buffer for transferring streams of data 失效
标题翻译：具有用于传送数据流的控制数据缓冲器的系统
公开(公告)号：US06732224B2
公开(公告)日：2004-05-04
申请号：US10449583
申请日：2003-05-30
申请人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
发明人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
IPC分类号： G11C804
CPC分类号： G09G5/391 , G11C7/103 , G11C7/1036 , G11C7/1072 , G11C7/1075 , H04B7/18502
摘要： A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
摘要翻译：公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。存储器电路（14）被串行和随机地访问。地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

3. 发明授权

US5680367A Process for controlling writing data to a DRAM array 失效
标题翻译：用于控制将数据写入DRAM阵列的处理
公开(公告)号：US5680367A
公开(公告)日：1997-10-21
申请号：US480637
申请日：1995-06-07
申请人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
发明人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
IPC分类号： G11C7/10 , G11C8/02 , H04B7/185 , G11C8/00
CPC分类号： G09G5/391 , G11C7/103 , G11C7/1036 , G11C7/1072 , G11C7/1075 , H04B7/18502
摘要： A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
摘要翻译：公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。存储器电路（14）被串行和随机地访问。地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

4. 发明授权

US4685135A Text-to-speech synthesis system 失效
标题翻译：文本到语音合成系统
公开(公告)号：US4685135A
公开(公告)日：1987-08-04
申请号：US240694
申请日：1981-03-05
申请人： Kun-Shan Lin , Kathleen M. Goudie , Gene A. Frantz
发明人： Kun-Shan Lin , Kathleen M. Goudie , Gene A. Frantz
IPC分类号： G10L13/08 , G10L5/00
CPC分类号： G10L13/08
摘要： A text-to-speech synthesis system receives digital code representative of characters from a local or remote source, and converts those character codes into speech. A set of allophone rules is contained in a memory and each incoming character set is matched with the proper character set to describe the sound of that particular character set. A microcontroller is dedicated to the comparison procedure which provides allophonic code when a match is made. The allophonic code is provided to a speech producing system which has a system microcontroller for controlling the retrieval, from a read-only memory, of digital signals representative of the individual allophone parameters. The addresses at which such allophone parameters are located are directly related to the allophonic code. A dedicated microcontroller concatenates the digital signals representative of the allophone parameters, including code indicating stress and intonation patterns for the allophones. An LPC speech synthesizer receives the digital signals and provides analog signals corresponding thereto to a loud speaker to produce speech-like sounds with stress and intonation.
摘要翻译：文本到语音合成系统从本地或远程源接收代表字符的数字代码，并将这些字符代码转换为语音。存储器中包含一组非音素规则，每个输入字符集与正确的字符集匹配，以描述该特定字符集的声音。一个微控制器专门用于比较程序，当进行匹配时，它提供了别的代码。提供给语音产生系统的语音产生系统，其具有系统微控制器，用于控制从只读存储器检索表示各个异音参数的数字信号的检索。这种异音素参数所在的地址与等离子体代码直接相关。专用微控制器连接表示异音素参数的数字信号，包括表示压力的代码和声调模式。 LPC语音合成器接收数字信号并提供与其对应的模拟信号给扬声器，以产生具有应力和语调的语音般的声音。

5. 发明授权

US4507750A Electronic apparatus from a host language 失效
标题翻译：来自主机语言的电子设备
公开(公告)号：US4507750A
公开(公告)日：1985-03-26
申请号：US377734
申请日：1982-05-13
申请人： Gene A. Frantz , Kun-Shan Lin
发明人： Gene A. Frantz , Kun-Shan Lin
IPC分类号： G06F17/28 , G06F15/38
CPC分类号： G06F17/28
摘要： An electronic apparatus for translation from a host language to a non-host language in which the individual word is evaluated as to its contextual meaning. The sequence of words, typically a sentence, within the host language, which is communicated to the electronic apparatus is translated, through a recognition device into a series of recognized words. These recognized words are further refined through analysis of their contextual meaning within the sequence (sentence) so as to differentiate between words of similar pronunciation and between homonyms. The present invention permits the direct entry, from voice, to a translator to a foreign language or alternatively to control language for use with an electronic or electromechanical apparatus.
摘要翻译：一种用于从主机语言到非主机语言的翻译的电子设备，其中对单词进行评估，其语境意义。通过识别装置将通信给电子设备的主机语言内的单词序列（通常为句子）翻译成一系列识别的单词。通过对序列（句子）中的语境意义进行分析，进一步改进这些识别的词，以便区分相似的发音和同音异义词。本发明允许从语音直接输入到翻译器到外语，或者替代地控制与电子机电设备一起使用的语言。

6. 发明授权

US4310831A Pulse width modulated, push/pull digital to analog converter 失效
标题翻译：脉冲宽度调制，推/拉数模转换器
公开(公告)号：US4310831A
公开(公告)日：1982-01-12
申请号：US118156
申请日：1980-02-04
申请人： Alva E. Henderson , Gene A. Frantz
发明人： Alva E. Henderson , Gene A. Frantz
IPC分类号： G09B19/06 , G10L13/04 , H03K9/08 , H03K13/02
CPC分类号： G10L13/047 , G09B19/06
摘要： A pulse width modulated digital-to-analog converter for utilization in low voltage, integrated circuit speech synthesis circuitry. A digitally programmable shift register is utilized to generate a pulse, which is generally related to the magnitude of a digital signal. A programmable delay circuit provides finer resolution by converting the least significant digital bits of data into pulse width information of shorter duration than the minimum pulse width generated by the controllable shift register. Pulse width information generated by the shift register and delay circuit is applied to the bases of two crossconnected transistors to drive a speaker or voice coil.
摘要翻译：一种用于低电压集成电路语音合成电路的脉宽调制数模转换器。数字可编程移位寄存器用于产生脉冲，其通常与数字信号的幅度相关。可编程延迟电路通过将数据的最低有效数字位转换成比由可控移位寄存器产生的最小脉冲宽度更短的持续时间的脉冲宽度信息来提供更精细的分辨率。由移位寄存器和延迟电路产生的脉冲宽度信息被施加到两个交叉连接的晶体管的基极以驱动扬声器或音圈。

7. 发明授权

US06895465B2 SDRAM with command decoder, address registers, multiplexer, and sequencer 有权
标题翻译： SDRAM具有命令解码器，地址寄存器，多路复用器和定序器
公开(公告)号：US06895465B2
公开(公告)日：2005-05-17
申请号：US10816076
申请日：2004-03-31
申请人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
发明人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
IPC分类号： G11C7/10 , G11C8/02 , H04B7/185 , G11C8/00 , G06F12/02
CPC分类号： G09G5/391 , G11C7/103 , G11C7/1036 , G11C7/1072 , G11C7/1075 , H04B7/18502
摘要： A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
摘要翻译：公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。存储器电路（14）被串行和随机地访问。地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

8. 发明授权

US06748483B2 Process of operating a DRAM system 失效
标题翻译：操作DRAM系统的过程
公开(公告)号：US06748483B2
公开(公告)日：2004-06-08
申请号：US10452744
申请日：2003-06-02
申请人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
发明人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
IPC分类号： G11C804
CPC分类号： G09G5/391 , G11C7/103 , G11C7/1036 , G11C7/1072 , G11C7/1075 , H04B7/18502
摘要： A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
摘要翻译：公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。存储器电路（14）被串行和随机地访问。地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

9. 发明授权

US06735668B2 Process of using a DRAM with address control data 失效
标题翻译：使用具有地址控制数据的DRAM的过程
公开(公告)号：US06735668B2
公开(公告)日：2004-05-11
申请号：US10452619
申请日：2003-06-02
申请人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
发明人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
IPC分类号： G11C804
CPC分类号： G09G5/391 , G11C7/103 , G11C7/1036 , G11C7/1072 , G11C7/1075 , H04B7/18502
摘要： A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).
摘要翻译：公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。存储器电路（14）被串行和随机地访问。地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

10. 发明授权

US06728828B2 Synchronous data transfer system 失效
标题翻译：同步数据传输系统
公开(公告)号：US06728828B2
公开(公告)日：2004-04-27
申请号：US10445134
申请日：2003-05-23
申请人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
发明人： Masashi Hashimoto , Gene A. Frantz , John Victor Moravec , Jean-Pierre Dolait
IPC分类号： G11C804
CPC分类号： G09G5/391 , G11C7/103 , G11C7/1036 , G11C7/1072 , G11C7/1075 , H04B7/18502
摘要： A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of the addresses is the random access address stored in the address buffer register (36).
摘要翻译：公开了具有特别适于允许存储器电路（14）用作视频帧存储器的特征的存储器电路（14）。存储器电路（14）包含在其输入和输出数据端口（22）上具有缓冲器（18,20）的动态随机存取存储器阵列（24），以允许对存储器阵列（24）的异步读取，写入和刷新访问。存储器电路（14）被串行和随机地访问。地址生成器（28）包含存储随机存取地址的地址缓冲寄存器（36）和向存储器阵列（24）提供地址流的地址定序器（40）。地址流的初始地址是存储在地址缓冲寄存器（36）中的随机存取地址。

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