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1. 发明申请

US20100057998A1 SNOOP REQUEST ARBITRATION IN A DATA PROCESSING SYSTEM 有权
标题翻译：数据处理系统中的SNOOP请求仲裁
公开(公告)号：US20100057998A1
公开(公告)日：2010-03-04
申请号：US12201225
申请日：2008-08-29
申请人： William C. Moyer , Quyen Pho
发明人： William C. Moyer , Quyen Pho
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F2212/1016
摘要： A snoop look-up operation is performed in a system having a cache and a first processor. The processor generates requests to the cache for data. A snoop queue is loaded with snoop requests. Fullness of the snoop queue is a measure of how many snoop requests are in the snoop queue. A snoop look-up operation is performed in the cache if the fullness of the snoop queue exceeds the threshold. The snoop look-up operation is based on a snoop request from the snoop queue corresponding to an entry in the snoop queue. If the fullness of the snoop queue does not exceed the threshold, waiting to perform a snoop look-up operation until an idle access request cycle from the processor to the cache occurs and performing the snoop look-up operation in the cache upon the idle access request cycle from the processor.
摘要翻译：在具有高速缓存和第一处理器的系统中执行窥探查找操作。处理器生成对高速缓存数据的请求。侦听队列加载了窥探请求。侦听队列的完整性是侦听队列中有多少个窥探请求的度量。如果侦听队列的充满度超过阈值，则在缓存中执行侦听查找操作。窥探查找操作基于来自与窥探队列中的条目相对应的窥探队列的窥探请求。如果侦听队列的充满度不超过阈值，则等待执行窥探查找操作，直到发生从处理器到高速缓存的空闲访问请求周期，并且在空闲访问时执行高速缓存中的窥探查找操作从处理器请求周期。

2. 发明授权

US08131951B2 Utilization of a store buffer for error recovery on a store allocation cache miss 有权
标题翻译：利用存储缓冲区对存储分配高速缓存未命中的错误恢复
公开(公告)号：US08131951B2
公开(公告)日：2012-03-06
申请号：US12130570
申请日：2008-05-30
申请人： William C. Moyer , Quyen Pho
发明人： William C. Moyer , Quyen Pho
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F9/3824 , G06F9/3863
摘要： A processor and cache is coupled to a system memory via a system interconnect. A first buffer circuit coupled to the cache receives one or more data words and stores the one or more data words in each of one or more entries. The one or more data words of a first entry are written to the cache in response to error free receipt. A second buffer circuit coupled to the cache has one or more entries for storing store requests. Each entry has an associated control bit that determines whether an entry formed from a first store request is a valid entry to be written to the system memory from the second buffer circuit. Based upon error free receipt of the one or more data words, the associated control bit is set to a value that invalidates the entry in the second buffer circuit based upon the error determination.
摘要翻译：处理器和高速缓存通过系统互连耦合到系统存储器。耦合到高速缓存的第一缓冲电路接收一个或多个数据字，并将一个或多个数据字存储在一个或多个条目的每一个中。响应于无错误的接收，将第一条目的一个或多个数据字写入高速缓存。耦合到高速缓存的第二缓冲电路具有用于存储存储请求的一个或多个条目。每个条目具有相关联的控制位，其确定从第一存储请求形成的条目是否是从第二缓冲电路写入系统存储器的有效条目。基于一个或多个数据字的无错误接收，相关联的控制位被设置为使得基于错误确定使第二缓冲电路中的条目无效的值。

3. 发明授权

US08131948B2 Snoop request arbitration in a data processing system 有权
标题翻译：在数据处理系统中侦听请求仲裁
公开(公告)号：US08131948B2
公开(公告)日：2012-03-06
申请号：US12201272
申请日：2008-08-29
申请人： William C. Moyer , Quyen Pho
发明人： William C. Moyer , Quyen Pho
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A snoop look-up operation is performed in a system having a first cache and a first processor. The first processor generates access requests to the first cache for data. Snoop look-up operations are performed in the cache. The snoop look-up operations are based on snoop requests from a snoop queue. The snoop requests correspond to entries in the snoop queue. An access request from the first processor is performed in response to a consecutive number of snoop look-up operations exceeding a first limit. This is useful in avoiding having no processor operations while performing snoop look-up operations. Similarly, consecutive access requests can be counted and if a second limit is exceeded, a snoop look-up operation can be performed.
摘要翻译：在具有第一高速缓存和第一处理器的系统中执行窥探查找操作。第一个处理器生成对第一个缓存的访问请求数据。 Snoop查找操作在缓存中执行。窥探查询操作基于来自侦听队列的窥探请求。侦听请求对应于侦听队列中的条目。响应于连续数量的窥探查找操作超过第一限制，执行来自第一处理器的访问请求。这对于在执行窥探查找操作时避免没有处理器操作非常有用。类似地，可以对连续的访问请求进行计数，并且如果超过第二限制，则可以执行窥探查找操作。

4. 发明授权

US09158725B2 Flexible control mechanism for store gathering in a write buffer 有权
公开(公告)号：US09158725B2
公开(公告)日：2015-10-13
申请号：US13682367
申请日：2012-11-20
申请人： William C. Moyer , Quyen Pho
发明人： William C. Moyer , Quyen Pho
IPC分类号： G06F13/40 , G06F12/04 , G06F9/38 , G06F9/30
CPC分类号： G06F13/4059 , G06F9/30043 , G06F9/3824 , G06F12/04 , Y02D10/13
摘要： A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address.

5. 发明授权

US09009411B2 Flexible control mechanism for store gathering in a write buffer 有权
标题翻译：灵活的控制机制，用于存储在写缓冲区中的采集
公开(公告)号：US09009411B2
公开(公告)日：2015-04-14
申请号：US13682350
申请日：2012-11-20
申请人： William C. Moyer , Quyen Pho
发明人： William C. Moyer , Quyen Pho
IPC分类号： G06F12/12 , G06F12/08
CPC分类号： G06F12/0895
摘要： A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address.
摘要翻译：在数据处理设备上启用或禁用存储收集策略。可以从多个商店收集策略中选择要由商店缓冲器实现的商店收集策略。例如，可以约束或不约束多个商店收集策略。存储收集策略可以由用户可编程存储位置启用。特定的商店收集策略可以由用户可编程存储位置指定。可以基于存储请求的属性（例如基于目的地地址）来确定商店收集策略。

6. 发明申请

US20140143500A1 FLEXIBLE CONTROL MECHANISM FOR STORE GATHERING IN A WRITE BUFFER 有权
标题翻译：用于存储缓存中存储的灵活控制机制
公开(公告)号：US20140143500A1
公开(公告)日：2014-05-22
申请号：US13682350
申请日：2012-11-20
申请人： William C. Moyer , Quyen Pho
发明人： William C. Moyer , Quyen Pho
IPC分类号： G06F12/12
CPC分类号： G06F12/0895
摘要： A store gathering policy is enabled or disabled at a data processing device. A store gathering policy to be implemented by a store buffer can be selected from a plurality of store gathering polices. For example, the plurality of store gathering policies can be constrained or unconstrained. A store gathering policy can be enabled by a user programmable storage location. A specific store gathering policy can be specified by a user programmable storage location. A store gathering policy can be determined based upon an attribute of a store request, such as based upon a destination address.
摘要翻译：在数据处理设备上启用或禁用存储收集策略。可以从多个商店收集策略中选择要由商店缓冲器实现的商店收集策略。例如，可以约束或不约束多个商店收集策略。存储收集策略可以由用户可编程存储位置启用。特定的商店收集策略可以由用户可编程存储位置指定。可以基于存储请求的属性（例如基于目的地地址）来确定商店收集策略。

7. 发明授权

US07987322B2 Snoop request management in a data processing system 有权
标题翻译：数据处理系统中的Snoop请求管理
公开(公告)号：US07987322B2
公开(公告)日：2011-07-26
申请号：US11969112
申请日：2008-01-03
申请人： William C. Moyer , Michael J. Rochford , Quyen Pho
发明人： William C. Moyer , Michael J. Rochford , Quyen Pho
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0831
摘要： Snoop requests are managed in a data processing system having a cache coupled to a processor that provides access addresses to the cache. Snoop queue circuitry provides snoop addresses to the cache via an arbiter. The snoop queue circuitry has a snoop request queue for storing a plurality of entries. Each entry of the snoop request queue that corresponds to a snoop request includes a snoop address and a corresponding status indicator. The corresponding status indicator indicates whether the snoop request has zero or more collapsed snoop requests having a common snoop address which have been merged to form the snoop request. The status indicator is used for debug and by fullness management logic to manage the capacity of the snoop request queue. A general collapsed status signal is generated to indicate whenever any snoop queue entry collapsing occurs.
摘要翻译：在具有耦合到提供高速缓存的访问地址的处理器的高速缓存的数据处理系统中管理侦听请求。侦听队列电路通过仲裁器向缓存提供窥探地址。侦听队列电路具有用于存储多个条目的窥探请求队列。与侦听请求对应的侦听请求队列的每个条目包括侦听地址和相应的状态指示符。相应的状态指示符指示窥探请求是否具有已经被合并以形成窥探请求的具有共同侦听地址的零个或多个收缩窥探请求。状态指示器用于调试和丰满度管理逻辑，以管理侦听请求队列的容量。生成通用的折叠状态信号，以指示何时发生任何侦听队列条目崩溃。

8. 发明申请

US20100058000A1 SNOOP REQUEST ARBITRATION IN A DATA PROCESSING SYSTEM 有权
标题翻译：数据处理系统中的SNOOP请求仲裁
公开(公告)号：US20100058000A1
公开(公告)日：2010-03-04
申请号：US12201272
申请日：2008-08-29
申请人： William C. Moyer , Quyen Pho
发明人： William C. Moyer , Quyen Pho
IPC分类号： G06F12/08
CPC分类号： G06F12/0831
摘要： A snoop look-up operation is performed in a system having a first cache and a first processor. The first processor generates access requests to the first cache for data. Snoop look-up operations are performed in the cache. The snoop look-up operations are based on snoop requests from a snoop queue. The snoop requests correspond to entries in the snoop queue. An access request from the first processor is performed in response to a consecutive number of snoop look-up operations exceeding a first limit. This is useful in avoiding having no processor operations while performing snoop look-up operations. Similarly, consecutive access requests can be counted and if a second limit is exceeded, a snoop look-up operation can be performed.
摘要翻译：在具有第一高速缓存和第一处理器的系统中执行窥探查找操作。第一个处理器生成对第一个缓存的访问请求数据。 Snoop查找操作在缓存中执行。窥探查询操作基于来自侦听队列的窥探请求。侦听请求对应于侦听队列中的条目。响应于连续数量的窥探查找操作超过第一限制，执行来自第一处理器的访问请求。这对于在执行窥探查找操作时避免没有处理器操作非常有用。类似地，可以对连续的访问请求进行计数，并且如果超过第二限制，则可以执行窥探查找操作。

9. 发明授权

US08291305B2 Error detection schemes for a cache in a data processing system 有权
标题翻译：数据处理系统中缓存的错误检测方案
公开(公告)号：US08291305B2
公开(公告)日：2012-10-16
申请号：US12205222
申请日：2008-09-05
申请人： William C. Moyer , Quyen Pho , Michael J. Rochford
发明人： William C. Moyer , Quyen Pho , Michael J. Rochford
IPC分类号： H03M13/00
CPC分类号： G06F11/1064 , H03M13/09 , H03M13/13
摘要： A method includes providing a cache; and providing a plurality of cache lines within the cache, wherein a first one of the plurality of cache lines has a tag entry and a data entry, wherein the tag entry has a parity field for storing one or more parity bits associated with a first portion of the tag entry, wherein the tag entry has an EDC field for storing one or more EDC check bits associated with a second portion of the tag entry and wherein the EDC check bits are used for detecting multiple bit errors, and wherein both the first parity field and the EDC field are stored in the tag entry of said first one of the plurality of cache lines.
摘要翻译：一种方法包括提供高速缓存; 并且在所述高速缓存中提供多个高速缓存线，其中所述多条高速缓存行中的第一条具有标签条目和数据条目，其中所述标签条目具有用于存储与第一部分相关联的一个或多个奇偶校验位的奇偶校验字段所述标签条目具有用于存储与所述标签条目的第二部分相关联的一个或多个EDC校验位的EDC字段，并且其中所述EDC校验位用于检测多个位错误，并且其中所述第一奇偶校验位字段和EDC字段存储在多个高速缓存线中的所述第一个高速缓存行的标签条目中。

10. 发明申请

US20090300294A1 UTILIZATION OF A STORE BUFFER FOR ERROR RECOVERY ON A STORE ALLOCATION CACHE MISS 有权
标题翻译：存储分配缓存错误恢复存储缓冲区的使用
公开(公告)号：US20090300294A1
公开(公告)日：2009-12-03
申请号：US12130570
申请日：2008-05-30
申请人： William C. Moyer , Quyen Pho
发明人： William C. Moyer , Quyen Pho
IPC分类号： G06F12/00
CPC分类号： G06F12/0859 , G06F9/3824 , G06F9/3863
摘要： A processor and cache is coupled to a system memory via a system interconnect. A first buffer circuit coupled to the cache receives one or more data words and stores the one or more data words in each of one or more entries. The one or more data words of a first entry are written to the cache in response to error free receipt. A second buffer circuit coupled to the cache has one or more entries for storing store requests. Each entry has an associated control bit that determines whether an entry formed from a first store request is a valid entry to be written to the system memory from the second buffer circuit. Based upon error free receipt of the one or more data words, the associated control bit is set to a value that invalidates the entry in the second buffer circuit based upon the error determination.
摘要翻译：处理器和高速缓存通过系统互连耦合到系统存储器。耦合到高速缓存的第一缓冲电路接收一个或多个数据字，并将一个或多个数据字存储在一个或多个条目的每一个中。响应于无错误的接收，将第一条目的一个或多个数据字写入高速缓存。耦合到高速缓存的第二缓冲电路具有用于存储存储请求的一个或多个条目。每个条目具有相关联的控制位，其确定从第一存储请求形成的条目是否是从第二缓冲电路写入系统存储器的有效条目。基于一个或多个数据字的无错误接收，相关联的控制位被设置为使得基于错误确定使第二缓冲电路中的条目无效的值。

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