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    • 4. 发明授权
    • Eyewear display and modules for same
    • 眼镜显示和模块相同
    • US08833571B2
    • 2014-09-16
    • US13027680
    • 2011-02-15
    • William Anderson
    • William Anderson
    • A47F7/02A47F5/00
    • A47F7/021A47F5/0087
    • An eyewear display including a plurality of pods. Each pod includes a pair of opposing sidewalls, a back wall, and a front wall to form a proximal opening. The front wall defines a plurality of apertures for receiving eyewear support fixtures. A base wall encloses a distal end of the pod to form a storage space for holding eyewear stock accessible by the proximal opening. A mounting mechanism attaches to the back wall by a hinge and has at least one mounting clip for coupling the pod to the display mounting fixture. Each pod is selectively pivotable away from the display mounting fixture to provide access to the storage space for restocking the eyewear display. Preferably, in a display position, the plurality of pods are arranged so that at least one of the proximal openings is at least partially blocked by an adjacent.
    • 一种眼镜显示器,包括多个荚。 每个荚包括一对相对的侧壁,后壁和形成近端开口的前壁。 前壁限定了用于接收眼镜支撑固定装置的多个孔。 底壁包围荚的远端以形成用于保持由近端开口可接近的眼用药物的储存空间。 安装机构通过铰链附接到后壁,并且具有至少一个用于将荚连接到显示器安装夹具的安装夹。 每个荚可以选择性地远离显示器安装夹具枢转,以提供对存储空间的访问以便重新储存眼镜显示器。 优选地,在显示位置,多个荚被布置成使得近侧开口中的至少一个至少部分被邻近的部分阻挡。
    • 10. 发明申请
    • System and method of using a predicate value to access a register file
    • 使用谓词值访问寄存器文件的系统和方法
    • US20060230257A1
    • 2006-10-12
    • US11104163
    • 2005-04-11
    • Muhammad AhmedErich PlondkeLucian CodrescuWilliam Anderson
    • Muhammad AhmedErich PlondkeLucian CodrescuWilliam Anderson
    • G06F9/30
    • G06F9/3842G06F9/3851G06F9/3885
    • A processor device is disclosed and includes a memory unit and at least one interleaved multi-threading instruction pipeline. The interleaved multi-threading instruction pipeline utilizes a number of clock cycles that is less than an instruction issue rate for each of a plurality of program threads that are stored within the memory unit. The memory unit includes six instruction caches. Further, the processor device includes six register files and each of the six register files is associated with one of the six instruction caches. Each of the plurality of program threads is associated with one of the six register files. Further, each of the six program threads includes a plurality of instructions and each of the plurality of instructions is stored within one of the six instruction caches of the memory.
    • 公开了处理器设备,并且包括存储器单元和至少一个交错多线程指令流水线。 交错多线程指令流水线利用小于存储在存储器单元内的多个程序线程中的每一个的指令发布速率的多个时钟周期。 存储单元包括六个指令高速缓存。 此外,处理器设备包括六个寄存器文件,六个寄存器文件中的每一个与六个指令高速缓存中的一个相关联。 多个程序线程中的每一个与六个寄存器文件中的一个相关联。 此外,六个程序线程中的每一个包括多个指令,并且多个指令中的每一个被存储在存储器的六个指令高速缓存之一中。