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1. 发明授权

US08094493B2 Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control 有权
标题翻译：使用改进的参考细胞修剪算法的存储器件和方法用于精确的读操作窗口控制
公开(公告)号：US08094493B2
公开(公告)日：2012-01-10
申请号：US11271300
申请日：2005-11-10
申请人： Wen-Yi Hsieh , Ken-Hui Chen , Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Ching-Chung Lin , Chuan-Ying Yu
发明人： Wen-Yi Hsieh , Ken-Hui Chen , Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Ching-Chung Lin , Chuan-Ying Yu
IPC分类号： G11C11/34 , G11C7/02
CPC分类号： G11C16/28 , G11C16/04 , G11C16/0475 , G11C29/028 , G11C29/24 , G11C29/50004 , G11C2211/5634
摘要： A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding reference line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).
摘要翻译：公开了一种存储器件，其包括多个字线和以多个模式之一工作并耦合到至少一个字线的多个存储单元。存储装置还包括多个参考线和参考单元。每个参考单元对应于一个操作模式，为相应模式提供参考电流，并耦合到至少一个参考线。来自参考单元的参考单元电流也可以与目标范围进行比较，并且如果在目标范围之外，可以相应地调整相应参考线上的电压电平，使得参考电流落在目标范围内（即，参考当前修剪）。

2. 发明申请

US20060104113A1 Memory devices and methods using improved reference cell trimming algorithms for accurate read operation window control 有权
标题翻译：使用改进的参考细胞修剪算法的存储器件和方法用于精确的读操作窗口控制
公开(公告)号：US20060104113A1
公开(公告)日：2006-05-18
申请号：US11271300
申请日：2005-11-10
申请人： Wen-Yi Hsieh , Ken-Hui Chen , Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Ching-Chung Lin , Chuan-Ying Yu
发明人： Wen-Yi Hsieh , Ken-Hui Chen , Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Ching-Chung Lin , Chuan-Ying Yu
IPC分类号： G11C16/06
CPC分类号： G11C16/28 , G11C16/04 , G11C16/0475 , G11C29/028 , G11C29/24 , G11C29/50004 , G11C2211/5634
摘要： A memory device is disclosed that includes a plurality of word lines and a plurality of memory cells operating in one of a plurality of modes and coupled to at least one of the word lines. The memory device also includes a plurality of reference lines and reference cells. Each reference cell corresponds to one of the operating modes, supplies a reference current for the corresponding mode, and is coupled to at least one of the reference lines. A reference cell current from a reference cell can also be compared to a target range and, if outside the target range, the voltage level on a corresponding referece line can be adjusted accordingly such that the reference current falls within the target range (i.e., reference current trimming).
摘要翻译：公开了一种存储器件，其包括多个字线和以多个模式之一工作并耦合到至少一个字线的多个存储单元。存储装置还包括多个参考线和参考单元。每个参考单元对应于一个操作模式，为相应模式提供参考电流，并耦合到至少一个参考线。来自参考单元的参考单元电流也可以与目标范围进行比较，并且如果在目标范围之外，可以相应地调整相应参考线上的电压电平，使得参考电流落在目标范围内（即，参考当前修剪）。

3. 发明申请

US20060279996A1 READ SOURCE LINE COMPENSATION IN A NON-VOLATILE MEMORY 有权
标题翻译：在非易失性存储器中读取源线补偿
公开(公告)号：US20060279996A1
公开(公告)日：2006-12-14
申请号：US11151168
申请日：2005-06-10
申请人： Chuan-Ying Yu , Nai-Ping Kuo , Ken-Hui Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chuan-Ying Yu , Nai-Ping Kuo , Ken-Hui Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/06
CPC分类号： G11C29/02 , G11C16/04 , G11C29/025 , G11C29/028 , G11C2029/5002
摘要： Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that is shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.
摘要翻译：根据本发明的非易失性存储器电路提供具有通过互连导体线在一组读出放大器之间共享的多个参考单元的参考存储器。每个参考存储器的较高数量的参考单元产生更大量的用于对多个源极线进行充电的电流。多个源极线耦合到互连导体条，用于与耦合到主存储器阵列中的存储器单元的源极线的电容匹配。在硅晶片出来之后，对由主存储器阵列中的源极线产生的电容的测量以及由参考阵列中的源极线产生的电容进行可选的修整。电容匹配的另一校准是通过切割源极线的一部分或者将一部分添加到源极线来修剪耦合到互连导体条和参考存储器的源极线之一来实现的。

4. 发明授权

US07180782B2 Read source line compensation in a non-volatile memory 有权
标题翻译：在非易失性存储器中读取源极线补偿
公开(公告)号：US07180782B2
公开(公告)日：2007-02-20
申请号：US11151168
申请日：2005-06-10
申请人： Chuan-Ying Yu , Nai-Ping Kuo , Ken-Hui Chen , Han-Sung Chen , Chun-Hsiung Hung
发明人： Chuan-Ying Yu , Nai-Ping Kuo , Ken-Hui Chen , Han-Sung Chen , Chun-Hsiung Hung
IPC分类号： G11C16/28
CPC分类号： G11C29/02 , G11C16/04 , G11C29/025 , G11C29/028 , G11C2029/5002
摘要： Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that are shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.
摘要翻译：根据本发明的非易失性存储器电路提供具有通过互连导体线在一组读出放大器之间共享的多个参考单元的参考存储器。每个参考存储器的较高数量的参考单元产生更大量的用于对多个源极线进行充电的电流。多个源极线耦合到互连导体条，用于与耦合到主存储器阵列中的存储器单元的源极线的电容匹配。在硅晶片出来之后，对由主存储器阵列中的源极线产生的电容的测量以及由参考阵列中的源极线产生的电容进行可选的修整。电容匹配的另一校准是通过切割源极线的一部分或者将一部分添加到源极线来修剪耦合到互连导体条和参考存储器的源极线之一来实现的。

5. 发明授权

US07295471B2 Memory device having a virtual ground array and methods using program algorithm to improve read margin loss 有权
标题翻译：具有虚拟接地阵列的存储器件和使用程序算法的方法来改善读取容差损失
公开(公告)号：US07295471B2
公开(公告)日：2007-11-13
申请号：US11273120
申请日：2005-11-14
申请人： Wen-Yi Hsieh , Nai-Ping Kuo , Chun-Hsiung Hung , Ken-Hui Chen
发明人： Wen-Yi Hsieh , Nai-Ping Kuo , Chun-Hsiung Hung , Ken-Hui Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/0475 , G11C16/28 , G11C16/3454 , G11C16/3459
摘要： A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified based on a first threshold state if leakage current is determined to pass through one or more neighboring memory cells. The programmed memory cell is verified based on a second threshold state if the leakage current is not determined to pass through one or more neighboring memory cells.
摘要翻译：具有包括多个存储单元的虚拟阵列的存储器件的程序验证方法确定漏电流是否通过一个或多个相邻的存储器单元到编程的存储器单元。如果确定泄漏电流通过一个或多个相邻存储器单元，则基于第一阈值状态来验证编程存储器单元。如果泄漏电流未被确定通过一个或多个相邻存储器单元，则基于第二阈值状态来验证编程存储器单元。

6. 发明申请

US20060267059A1 Peripheral circuit architecture for array memory 审中-公开
标题翻译：阵列存储器的外围电路架构
公开(公告)号：US20060267059A1
公开(公告)日：2006-11-30
申请号：US11137098
申请日：2005-05-25
申请人： Chuan-Ying Yu , Chun-Hsiung Hung , Su-Chueh Lo , Nai-Ping Kuo , Ken-Hui Chen
发明人： Chuan-Ying Yu , Chun-Hsiung Hung , Su-Chueh Lo , Nai-Ping Kuo , Ken-Hui Chen
IPC分类号： H01L29/94
CPC分类号： H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898
摘要： A wordline driver cell, coupled to at least one wordline, includes at least one diffusion region and at least one wordline driver semiconductor switching device formed in the at least one diffusion region. The at least one wordline driver semiconductor switching device has a channel width that is arranged perpendicular to a longitudinal axis of the at least one wordline.
摘要翻译：耦合到至少一个字线的字线驱动器单元包括形成在至少一个扩散区域中的至少一个扩散区域和至少一个字线驱动器半导体开关器件。所述至少一个字线驱动器半导体开关器件具有垂直于所述至少一个字线的纵向轴线布置的沟道宽度。

7. 发明申请

US20060109710A1 Memory device having a virtual ground array and methods using program algorithm to improve read margin loss 有权
标题翻译：具有虚拟接地阵列的存储器件和使用程序算法的方法来改善读取容差损失
公开(公告)号：US20060109710A1
公开(公告)日：2006-05-25
申请号：US11273120
申请日：2005-11-14
申请人： Wen-Yi Hsieh , Nai-Ping Kuo , Chun-Hsiung Hung , Ken-Hui Chen
发明人： Wen-Yi Hsieh , Nai-Ping Kuo , Chun-Hsiung Hung , Ken-Hui Chen
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C16/28 , G11C16/3454 , G11C16/3459
摘要： A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified based on a first threshold state if leakage current is determined to pass through one or more neighboring memory cells. The programmed memory cell is verified based on a second threshold state if the leakage current is not determined to pass through one or more neighboring memory cells.
摘要翻译：具有包括多个存储单元的虚拟阵列的存储器件的程序验证方法确定漏电流是否通过一个或多个相邻的存储器单元到编程的存储器单元。如果确定泄漏电流通过一个或多个相邻存储器单元，则基于第一阈值状态来验证编程存储器单元。如果泄漏电流未被确定通过一个或多个相邻存储器单元，则基于第二阈值状态来验证编程存储器单元。

8. 发明授权

US07289359B2 Systems and methods for using a single reference cell in a dual bit flash memory 有权
标题翻译：在双位闪存中使用单个参考单元的系统和方法
公开(公告)号：US07289359B2
公开(公告)日：2007-10-30
申请号：US11223357
申请日：2005-09-09
申请人： Nai-Ping Kuo , Han-Sung Chen , Ken-Hui Chen , Chun-Hsiung Hung
发明人： Nai-Ping Kuo , Han-Sung Chen , Ken-Hui Chen , Chun-Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C16/28 , G11C16/0475
摘要： A dual bit flash device comprising a core cell array, each cell of the core cell array is configured to store two bits of data, and a single reference array, each cell of the single reference array comprising a first bit programmed to a low threshold voltage and a second bit programmed to a high threshold voltage.
摘要翻译：一种双位闪存器件，包括核心单元阵列，所述核心单元阵列的每个单元被配置为存储两位数据，以及单个参考阵列，所述单个参考阵列的每个单元包括被编程为低阈值电压的第一位并且被编程为高阈值电压的第二位。

9. 发明申请

US20070058439A1 Systems and methods for a reference circuit in a dual bit flash memory device 有权
标题翻译：双位闪存器件中的参考电路的系统和方法
公开(公告)号：US20070058439A1
公开(公告)日：2007-03-15
申请号：US11223357
申请日：2005-09-09
申请人： Nai-Ping Kuo , Han-Sung Chen , Ken-Hui Chen , Chun-Hsiung Hung
发明人： Nai-Ping Kuo , Han-Sung Chen , Ken-Hui Chen , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C16/28 , G11C16/0475
摘要： A dual bit flash device comprising a core cell array, each cell of the core cell array is configured to store two bits of data, and a single reference array, each cell of the single reference array comprising a first bit programmed to a low threshold voltage and a second bit programmed to a high threshold voltage.
摘要翻译：一种双位闪存器件，包括核心单元阵列，所述核心单元阵列的每个单元被配置为存储两位数据，以及单个参考阵列，所述单个参考阵列的每个单元包括被编程为低阈值电压的第一位并且被编程为高阈值电压的第二位。

10. 发明授权

US07830723B2 Nitride read-only memory cell and nitride read-only memory array 有权
标题翻译：氮化物只读存储单元和氮化物只读存储器阵列
公开(公告)号：US07830723B2
公开(公告)日：2010-11-09
申请号：US12423013
申请日：2009-04-14
申请人： Wen-Yi Hsieh , Ching-Chung Lin , Ken-Hui Chen , Chun-Hsiung Hung
发明人： Wen-Yi Hsieh , Ching-Chung Lin , Ken-Hui Chen , Chun-Hsiung Hung
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/0475 , G11C16/04 , G11C16/3445 , G11C29/50 , G11C29/50004 , G11C29/52
摘要： A NROM memory device includes an array of memory cells and first and second bit lines. The first and second bit lines are coupled to opposite sides of the memory cells. During an erase operation, one of the sides of the memory cells receives a positive voltage and the other side couples to a common node or a limited current source. Methods are also disclosed that can easily screen for marginal memory cells based on a threshold voltage distribution of the memory cells.
摘要翻译： NROM存储器件包括存储器单元阵列和第一和第二位线。第一和第二位线耦合到存储器单元的相对侧。在擦除操作期间，存储器单元的一侧接收正电压，另一侧耦合到公共节点或有限电流源。还公开了可以容易地基于存储器单元的阈值电压分布来筛选边际存储器单元的方法。

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