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1. 发明授权

US07084687B2 Phase swallow device and signal generator using the same 有权
标题翻译：相位吞咽装置和信号发生器使用相同
公开(公告)号：US07084687B2
公开(公告)日：2006-08-01
申请号：US10896118
申请日：2004-07-22
申请人： Wen-Shiung Weng , Ming-Chun Chang , Chi-Kung Kuan , Yi-Shu Chang , Kuo-Lin Tai
发明人： Wen-Shiung Weng , Ming-Chun Chang , Chi-Kung Kuan , Yi-Shu Chang , Kuo-Lin Tai
IPC分类号： G06F1/04
CPC分类号： G06F1/10 , H03L7/00
摘要： A signal generator for generating a clock with lower jitter. The signal generator includes a multi-phase clock generator for generating a plurality of multi-phase reference clocks with same frequency, a multiplexer for selecting one reference clock as an output clock according to a phase selecting signal, a phase-swallow control unit having a comparator for comparing a swallow value with a reference value out of order and outputting the comparing result as a swallow control signal, and a clock selector for receiving the swallow control signal and generating the phase selecting signal. Because the reference value is provided by a counter in bit-reversed, the swallow control signal is dispersed smoothly and the jitter of the output clock is reduced.
摘要翻译：用于产生具有较低抖动的时钟的信号发生器。信号发生器包括用于产生具有相同频率的多个多相参考时钟的多相时钟发生器，用于根据相位选择信号选择一个参考时钟作为输出时钟的多路复用器，具有相位选择信号的相位控制单元比较器，用于将吞咽值与参考值进行比较，并输出比较结果作为吞咽控制信号;以及时钟选择器，用于接收吞咽控制信号并产生相位选择信号。由于参考值由位反转的计数器提供，所以吞咽控制信号平滑地分散，并且输出时钟的抖动减小。

2. 发明申请

US20050017771A1 Phase swallow device and signal generator using the same 有权
标题翻译：相位吞咽装置和信号发生器使用相同
公开(公告)号：US20050017771A1
公开(公告)日：2005-01-27
申请号：US10896118
申请日：2004-07-22
申请人： Wen-Shiung Weng , Ming-Chun Chang , Chi-Kung Kuan , Yi-Shu Chang , Kuo-Lin Tai
发明人： Wen-Shiung Weng , Ming-Chun Chang , Chi-Kung Kuan , Yi-Shu Chang , Kuo-Lin Tai
IPC分类号： G06F1/10 , H03L7/00
CPC分类号： G06F1/10 , H03L7/00
摘要： A signal generator for generating a clock with lower jitter. The signal generator includes a multi-phase clock generator for generating a plurality of multi-phase reference clocks with same frequency, a multiplexer for selecting one reference clock as an output clock according to a phase selecting signal, a phase-swallow control unit having a comparator for comparing a swallow value with a reference value out of order and outputting the comparing result as a swallow control signal, and a clock selector for receiving the swallow control signal and generating the phase selecting signal. Because the reference value is provided by a counter in bit-reversed, the swallow control signal is dispersed smoothly and the jitter of the output clock is reduced.
摘要翻译：用于产生具有较低抖动的时钟的信号发生器。信号发生器包括用于产生具有相同频率的多个多相参考时钟的多相时钟发生器，用于根据相位选择信号选择一个参考时钟作为输出时钟的多路复用器，具有相位选择信号的相位控制单元比较器，用于将吞咽值与参考值进行比较，并输出比较结果作为吞咽控制信号;以及时钟选择器，用于接收吞咽控制信号并产生相位选择信号。由于参考值由位反转的计数器提供，所以吞咽控制信号平滑地分散，并且输出时钟的抖动减小。

3. 发明申请

US20050055597A1 Clock tuning device and method 失效
标题翻译：时钟调谐装置及方法
公开(公告)号：US20050055597A1
公开(公告)日：2005-03-10
申请号：US10933896
申请日：2004-09-03
申请人： Wen-Shiung Weng , Chi-Kung Kuan , Sheng-Kai Chen , Ming-Chun Chang , Yi-Shu Chang
发明人： Wen-Shiung Weng , Chi-Kung Kuan , Sheng-Kai Chen , Ming-Chun Chang , Yi-Shu Chang
IPC分类号： G06F1/04 , G06F1/08
CPC分类号： G06F1/08
摘要： A clock tuning device and method for executing overclocking operations on plural elements disposed on a motherboard. The clock tuning device includes a phase-locked loop for outputting a plurality of clock signals to the elements, and a control circuit for controlling the phase-locked loop to adjust the frequencies of the clock signals, so as to execute the overclocking operations on the elements, respectively. The method includes the steps of: increasing the frequency of a first clock signal until one of the elements can't work normally due to an utmost frequency of the first clock signal; resetting all the elements and operating the element corresponding to the first signal according to a safe frequency of the first clock signal; and repeating the above steps to perform overclocking operation on each of the other elements.
摘要翻译：一种用于对设置在母板上的多个元件执行超频操作的时钟调谐装置和方法。时钟调谐装置包括用于向元件输出多个时钟信号的锁相环，以及用于控制锁相环以调整时钟信号的频率的控制电路，以便对该时钟信号执行超频操作元素。该方法包括以下步骤：增加第一时钟信号的频率，直到其中一个元件由于第一时钟信号的最大频率而不能正常工作; 根据第一时钟信号的安全频率，复位所有元件并对与第一信号相对应的元件进行操作; 并重复上述步骤对每个其他元件执行超频操作。

4. 发明授权

US07249275B2 Clock generating device and method for executing overclocking operation 失效
标题翻译：用于执行超频操作的时钟产生装置和方法
公开(公告)号：US07249275B2
公开(公告)日：2007-07-24
申请号：US10933896
申请日：2004-09-03
申请人： Wen-Shiung Weng , Chi-Kung Kuan , Sheng-Kai Chen , Ming-Chun Chang , Yi-Shu Chang
发明人： Wen-Shiung Weng , Chi-Kung Kuan , Sheng-Kai Chen , Ming-Chun Chang , Yi-Shu Chang
IPC分类号： G06F1/10
CPC分类号： G06F1/08
摘要： A clock tuning device and method for executing overclocking operations on plural elements disposed on a motherboard. The clock tuning device includes a phase-locked loop for outputting a plurality of clock signals to the elements, and a control circuit for controlling the phase-locked loop to adjust the frequencies of the clock signals, so as to execute the overclocking operations on the elements, respectively. The method includes the steps of: increasing the frequency of a first clock signal until one of the elements can't work normally due to an utmost frequency of the first clock signal; resetting all the elements and operating the element corresponding to the first signal according to a safe frequency of the first clock signal; and repeating the above steps to perform overclocking operation on each of the other elements.
摘要翻译：一种用于对设置在母板上的多个元件执行超频操作的时钟调谐装置和方法。时钟调谐装置包括用于向元件输出多个时钟信号的锁相环，以及用于控制锁相环以调整时钟信号的频率的控制电路，以便对该时钟信号执行超频操作元素。该方法包括以下步骤：增加第一时钟信号的频率，直到其中一个元件由于第一时钟信号的最大频率而不能正常工作; 根据第一时钟信号的安全频率，复位所有元件并对与第一信号相对应的元件进行操作; 并重复上述步骤对每个其他元件执行超频操作。

5. 发明申请

US20060098948A1 VIDEO PROCESSING APPARATUS AND METHOD THEREOF 有权
标题翻译：视频处理装置及其方法
公开(公告)号：US20060098948A1
公开(公告)日：2006-05-11
申请号：US11164066
申请日：2005-11-09
申请人： Cheng-Shun Liao , Chia-Pei Chang , Yi-Shu Chang , Ming-Chun Chang
发明人： Cheng-Shun Liao , Chia-Pei Chang , Yi-Shu Chang , Ming-Chun Chang
IPC分类号： H04N5/781
CPC分类号： H04N21/4884 , H04N5/44504 , H04N9/641 , H04N21/23614 , H04N21/4348
摘要： A video processing apparatus includes: a line-based data encoder for performing line-based data encoding on an input signal to generate a line-based data encoded signal; and a video signal controller coupled to the line-based data encoder for receiving a first video signal and the line-based data encoded signal, decoding the line-based data encoded signal to generate a second video signal, and choosing one of the first and second video signals to generate an output signal.
摘要翻译：视频处理装置包括：基于行的数据编码器，用于对输入信号执行基于行的数据编码，以生成基于行的数据编码信号; 以及视频信号控制器，其耦合到所述基于线路的数据编码器，用于接收第一视频信号和所述基于行的数据编码信号，对所述基于线的数据编码信号进行解码以产生第二视频信号，以及选择所述第一和第二视频信号以产生输出信号。

6. 发明授权

US07675576B2 Video processing apparatus and method thereof 有权
标题翻译：视频处理装置及其方法
公开(公告)号：US07675576B2
公开(公告)日：2010-03-09
申请号：US11164066
申请日：2005-11-09
申请人： Cheng-Shun Liao , Chia-Pei Chang , Yi-Shu Chang , Ming-Chun Chang
发明人： Cheng-Shun Liao , Chia-Pei Chang , Yi-Shu Chang , Ming-Chun Chang
IPC分类号： H04N7/00 , H04N11/00 , H04N5/50 , H04N9/76
CPC分类号： H04N21/4884 , H04N5/44504 , H04N9/641 , H04N21/23614 , H04N21/4348
摘要： A video processing apparatus includes: a line-based data encoder for performing line-based data encoding on an input signal to generate a line-based data encoded signal; and a video signal controller coupled to the line-based data encoder for receiving a first video signal and the line-based data encoded signal, decoding the line-based data encoded signal to generate a second video signal, and choosing one of the first and second video signals to generate an output signal.
摘要翻译：视频处理装置包括：基于行的数据编码器，用于对输入信号执行基于行的数据编码，以生成基于行的数据编码信号; 以及视频信号控制器，其耦合到所述基于线路的数据编码器，用于接收第一视频信号和所述基于线路的数据编码信号，对所述基于线的数据编码信号进行解码以产生第二视频信号，以及选择所述第一和第二视频信号以产生输出信号。

7. 发明申请

US20130024167A1 Computer-Implemented Systems And Methods For Large Scale Automatic Forecast Combinations 审中-公开
标题翻译：计算机实施的大规模自动预测组合系统和方法
公开(公告)号：US20130024167A1
公开(公告)日：2013-01-24
申请号：US13189131
申请日：2011-07-22
申请人： Edward Tilden Blair , Michael J. Leonard , David Bruce Elsheimer , Jerzy Michal Brzezicki , Kannukuzhiyil Kurien Kurien , Michael Ryan Chipley , Dinesh P. Apte , Ming-Chun Chang
发明人： Edward Tilden Blair , Michael J. Leonard , David Bruce Elsheimer , Jerzy Michal Brzezicki , Kannukuzhiyil Kurien Kurien , Michael Ryan Chipley , Dinesh P. Apte , Ming-Chun Chang
IPC分类号： G06F17/10
CPC分类号： G06F17/18 , G06Q10/04
摘要： Systems and methods are provided for evaluating a physical process with respect to one or more attributes of the physical process by combining forecasts for the one or more physical process attributes, where data for evaluating the physical process is generated over time. A forecast model selection graph is accessed, the forecast model selection graph comprising a hierarchy of nodes arranged in parent-child relationships. A plurality of model forecast nodes are resolved, where resolving a model forecast node includes generating a node forecast for the one or more physical process attributes. A combination node is processed, where a combination node transforms a plurality of node forecasts at child nodes of the combination node into a combined forecast. A selection node is processed, where a selection node chooses a node forecast from among child nodes of the selection node based on a selection criteria.
摘要翻译：提供了系统和方法，用于通过组合用于一个或多个物理过程属性的预测来结合物理过程的一个或多个属性来评估物理过程，其中用于评估物理过程的数据随时间生成。访问预测模式选择图，预测模型选择图包括在父子关系中排列的节点的层次结构。分解多个模型预测节点，其中解析模型预测节点包括为一个或多个物理过程属性生成节点预测。处理组合节点，其中组合节点将组合节点的子节点处的多个节点预测转换为组合预测。处理选择节点，其中选择节点基于选择标准从选择节点的子节点中选择节点预测。

8. 发明授权

US07710435B2 Method and apparatus for generating visual effects 有权
标题翻译：用于产生视觉效果的方法和装置
公开(公告)号：US07710435B2
公开(公告)日：2010-05-04
申请号：US11161949
申请日：2005-08-23
申请人： Zou-Ping Chen , Cheng-Shun Liao , Ming-Chun Chang
发明人： Zou-Ping Chen , Cheng-Shun Liao , Ming-Chun Chang
IPC分类号： G09G5/02
CPC分类号： H04N9/74
摘要： A visual effect generating module for changing visual effects of a selected image block within an image area is disclosed. The visual effect generating module includes a color changing module for receiving and changing pixel values of a plurality of pixels within the selected image block and a first multiplexer coupled to the color changing module for selectively outputting pixels corresponding to the image area or pixels output from the color changing module.
摘要翻译：公开了一种用于在图像区域内改变所选择的图像块的视觉效果的视觉效果产生模块。该视觉效果产生模块包括：颜色改变模块，用于接收和改变所选择的图像块内的多个像素的像素值;以及第一多路复用器，耦合到颜色变化模块，用于选择性地输出与图像区域对应的像素或从换色模块

9. 发明授权

US07716022B1 Computer-implemented systems and methods for processing time series data 有权
标题翻译：用于处理时间序列数据的计算机实现的系统和方法
公开(公告)号：US07716022B1
公开(公告)日：2010-05-11
申请号：US11431116
申请日：2006-05-09
申请人： Youngjin Park , Michael J. Leonard , Rajesh S. Selukar , Ming-Chun Chang
发明人： Youngjin Park , Michael J. Leonard , Rajesh S. Selukar , Ming-Chun Chang
IPC分类号： G06F17/10
CPC分类号： G06Q10/10 , G06F17/18 , G06Q30/0201 , G06Q30/0202
摘要： Computer-implemented systems and methods for providing a forecast using time series data that is indicative of a data generation activity occurring over a period of time. Candidate models and candidate input variables are received. For each candidate model, transfer functions are determined for the candidate input variables in order to relate a variable to be forecasted to the time series data. For each candidate model there is a selection of which of the candidate input variables to include in each of the candidate models based upon the determined transfer functions. A model is selected from the candidate models to forecast the time series data using the selected input variables of the selected model.
摘要翻译：用于使用指示在一段时间内发生的数据生成活动的时间序列数据来提供预测的计算机实现的系统和方法。接收候选模型和候选输入变量。对于每个候选模型，为候选输入变量确定传递函数，以便将要预测的变量与时间序列数据相关联。对于每个候选模型，基于所确定的传递函数，选择要在每个候选模型中包括哪些候选输入变量。从候选模型中选择模型，使用所选模型的选定输入变量预测时间序列数据。

10. 发明授权

US07583124B2 Delaying stage selecting circuit and method thereof 有权
标题翻译：延迟阶段选择电路及其方法
公开(公告)号：US07583124B2
公开(公告)日：2009-09-01
申请号：US12019645
申请日：2008-01-25
申请人： Tung-Chen Kuo , Ming-Chun Chang
发明人： Tung-Chen Kuo , Ming-Chun Chang
IPC分类号： H03H11/26
CPC分类号： H03K5/131 , H03K5/133 , H03K2005/00058 , H03K2005/00234
摘要： A delaying stage selecting circuit for selecting a specific delaying stage from a plurality of delaying stages, where the delaying stages are for outputting delayed clock signals, includes: a first register for sampling the delayed clock signals according to a clock signal to generate sampled values; first memory units, wherein the first memory units are utilized to memorize the sampled values, and each of first memory unit outputs at least one of the sampled values according to a corresponding first selecting signal; a first selecting unit, for outputting the sampled values according to a second selecting signal; a determining module, for determining if the sampled values meet a specific relation, where if the determination result is positive then determining the particular delaying stage; and a counter for generating a counting value to control the delayed clock signal sampled by the first register.
摘要翻译：延迟级选择电路，用于从延迟级用于输出延迟时钟信号的多个延迟级中选择特定的延迟级，包括：第一寄存器，用于根据时钟信号对延迟的时钟信号进行采样以产生采样值; 第一存储器单元，其中第一存储器单元用于存储采样值，并且每个第一存储器单元根据对应的第一选择信号输出采样值中的至少一个; 第一选择单元，用于根据第二选择信号输出采样值; 确定模块，用于确定所述采样值是否满足特定关系，其中如果所述确定结果为正，则确定所述特定延迟级; 以及用于产生计数值以控制由第一寄存器采样的延迟时钟信号的计数器。

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