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1. 发明授权

US06691214B1 DDR II write data capture calibration 失效
公开(公告)号：US06691214B1
公开(公告)日：2004-02-10
申请号：US09650079
申请日：2000-08-29
申请人： Wen Li , Christopher K. Morzano
发明人： Wen Li , Christopher K. Morzano
IPC分类号： G06F1200
CPC分类号： G11C7/1078 , G11C7/02 , G11C7/1006 , G11C7/1066 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4096 , G11C2207/107 , G11C2207/2254
摘要： A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., “1100,” is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined pattern and adjusts a delay applied to the data signal until the predetermined pattern is recognized. Then the delay is further adjusted until the predetermined pattern is no longer recognized indicating that an edge of the eye of the data is near a clocking edge of the clocking signal. The delay applied to the data signal is then further adjusted by a predetermined amount to position the clock edge near the center of the data eye.

2. 发明授权

US07561477B2 Data strobe synchronization circuit and method for double data rate, multi-bit writes 有权
标题翻译：数据选通同步电路和方法，用于双倍数据速率，多位写入
公开(公告)号：US07561477B2
公开(公告)日：2009-07-14
申请号：US12077878
申请日：2008-03-20
申请人： Christopher K. Morzano , Wen Li
发明人： Christopher K. Morzano , Wen Li
IPC分类号： G11C7/10 , G11C8/00
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C11/4076 , G11C11/4094
摘要： A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe pulse responsive to each global data strobe pulse. The control circuit receives a write control signal. When the write control signal becomes active, the control circuit terminates the enable signal applied to the first logic circuit and applies an enable signal to the second logic circuit. The second logic circuit then generates a second data strobe pulse responsive to the next global data strobe pulse. The first and second data strobe pulses are used to latch a data signal in respective flip-flops. The data strobe pulses may latch the data signal in pairs of flip-flops on the leading and trailing edges of the data strobe pulses.
摘要翻译：数据选通同步电路包括接收全局数据选通脉冲的第一和第二逻辑电路和相应的使能信号。控制电路首先向第一逻辑电路施加使能信号，使得第一逻辑电路响应于每个全局数据选通脉冲产生第一数据选通脉冲。控制电路接收写入控制信号。当写入控制信号变为有效时，控制电路终止施加到第一逻辑电路的使能信号并向第二逻辑电路施加使能信号。然后，第二逻辑电路响应于下一个全局数据选通脉冲产生第二数据选通脉冲。第一和第二数据选通脉冲用于锁存相应触发器中的数据信号。数据选通脉冲可以在数据选通脉冲的前沿和后沿成对的触发器锁存数据信号。

3. 发明授权

US07054222B2 Write address synchronization useful for a DDR prefetch SDRAM 有权
公开(公告)号：US07054222B2
公开(公告)日：2006-05-30
申请号：US10894269
申请日：2004-07-19
申请人： Wen Li , Christopher K. Morzano
发明人： Wen Li , Christopher K. Morzano
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C7/1078 , G11C7/1093
摘要： Disclosed herein are exemplary embodiments of an improved write address shift register structure useful for example in a DDR3 DRAM having read/write latency. The disclosed shift register structure propagates write addresses from an address bus outside the device to array decoders to allow latent data to be written into the cells in the memory array at a proper time. The register structure comprises a reduced number of registers (e.g., four) thus eliminating the need for extraneous registers which might otherwise be used to propagate “don't care” addresses. The registers are clocked, and the addresses propagated though the registers, in accordance with a latency bus through which a user defines the desired read/write latency in accordance with user preferences and the desired clock speed of the device. The clock for each register is preferably decoded from the latency bus and hence each register preferably has its own unique clock.

4. 发明授权

US06600691B2 High frequency range four bit prefetch output data path 有权
公开(公告)号：US06600691B2
公开(公告)日：2003-07-29
申请号：US10207641
申请日：2002-07-29
申请人： Christopher K. Morzano , Wen Li
发明人： Christopher K. Morzano , Wen Li
IPC分类号： G11C700
CPC分类号： G11C7/1066 , G11C7/1012 , G11C7/1039 , G11C7/1051 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4096 , G11C2207/2281
摘要： A method of transferring a plurality of data bits from memory cells to a data pad via a plurality of output paths. Each of the output paths receives the data bits in parallel and selects one bit among the data bits. Selected bits from each of the output paths is transferred to an output select. A plurality of timing signals are activated in sequence based on alternate phases of two enable signals to serially transfer the data bits from the output select to the data pad.

5. 发明申请

US20100289678A1 Parallel-to-serial data sort device 审中-公开
标题翻译：并行到串行数据排序设备
公开(公告)号：US20100289678A1
公开(公告)日：2010-11-18
申请号：US12804278
申请日：2010-07-19
申请人： Christopher K Morzano , Wen Li
发明人： Christopher K Morzano , Wen Li
IPC分类号： H03M9/00
CPC分类号： G11C7/1051 , G11C7/10 , G11C7/1012 , G11C2207/107 , H03M9/00
摘要： A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals.
摘要翻译：公开并提供了用于将并行数据转换为串行数据的数据分类装置。数据分类装置可以包括用于接收并行数据的多个开关，每个开关由相应的控制信号控制，并被配置为交替地发送经由第一和第二输入端接收的数据位。

6. 发明授权

US07525458B2 Method and apparatus for converting parallel data to serial data in high speed applications 失效
标题翻译：在高速应用中将并行数据转换为串行数据的方法和装置
公开(公告)号：US07525458B2
公开(公告)日：2009-04-28
申请号：US12033763
申请日：2008-02-19
申请人： Christopher K. Morzano , Wen Li
发明人： Christopher K. Morzano , Wen Li
IPC分类号： H03M9/00
CPC分类号： G11C7/1051 , G11C7/10 , G11C7/1012 , G11C2207/107 , H03M9/00
摘要： A method and apparatus to convert parallel data to serial data is provided. More specifically, there is provided a parallel-to-serial converter comprising a data pipeline configured to receive parallel data, and binary sort logic comprising a plurality of switches arranged to receive the parallel data from the data pipeline, and configured to output the parallel data serially.
摘要翻译：提供了一种将并行数据转换为串行数据的方法和装置。更具体地，提供了一种并行 - 串行转换器，其包括被配置为接收并行数据的数据流水线，以及二进制排序逻辑，其包括多个开关，其被布置为从数据流水线接收并行数据，并且被配置为输出并行数据连续地

7. 发明申请

US20080181031A1 Data strobe synchronization circuit and method for double data rate, multi-bit writes 有权
公开(公告)号：US20080181031A1
公开(公告)日：2008-07-31
申请号：US12077878
申请日：2008-03-20
申请人： Christopher K. Morzano , Wen Li
发明人： Christopher K. Morzano , Wen Li
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C11/4076 , G11C11/4094
摘要： A data strobe synchronization circuit includes first and second logic circuits receiving global data strobe pulses and respective enable signal. A control circuit initially applies an enable signal to the first logic circuit so that the first logic circuit generates a first data strobe pulse responsive to each global data strobe pulse. The control circuit receives a write control signal. When the write control signal becomes active, the control circuit terminates the enable signal applied to the first logic circuit and applies an enable signal to the second logic circuit. The second logic circuit then generates a second data strobe pulse responsive to the next global data strobe pulse. The first and second data strobe pulses are used to latch a data signal in respective flip-flops. The data strobe pulses may latch the data signal in pairs of flip-flops on the leading and trailing edges of the data strobe pulses.

8. 发明授权

US06532180B2 Write data masking for higher speed DRAMs 失效
标题翻译：为更高速的DRAM写入数据屏蔽
公开(公告)号：US06532180B2
公开(公告)日：2003-03-11
申请号：US09883957
申请日：2001-06-20
申请人： Kevin J. Ryan , Christopher K. Morzano , Wen Li
发明人： Kevin J. Ryan , Christopher K. Morzano , Wen Li
IPC分类号： G11C700
CPC分类号： G11C7/1078 , G11C7/1006 , G11C11/4087 , G11C11/4096
摘要： A method and apparatus for masking data written to a memory device that reduces the effective write cycle time of the memory device is disclosed. Firing of the column selects is pre-empted, thereby masking data to be written to a memory device. By pre-empting the column selects, the margin required for disabling a write driver can be eliminated, thereby reducing the effective write cycle. Additionally, data masking can be performed on a per-byte basis by associating independent column selects with each data byte on multi-byte wide devices, e.g., ×16 or ×32.
摘要翻译：公开了一种用于掩蔽写入存储器件的数据的方法和装置，其减少了存储器件的有效写周期时间。列选择的触发被抢占，从而掩蔽要写入存储器件的数据。通过预先排除列选择，可以消除禁用写驱动程序所需的余量，从而减少有效的写周期。另外，通过将独立列选择与多字节宽的器件上的每个数据字节（例如x16或x32）相关联，可以在每个字节的基础上执行数据屏蔽。

9. 发明授权

US07764206B2 Parallel-to-serial data sort device 有权
标题翻译：并行到串行数据排序设备
公开(公告)号：US07764206B2
公开(公告)日：2010-07-27
申请号：US12427577
申请日：2009-04-21
申请人： Christopher K. Morzano , Wen Li
发明人： Christopher K. Morzano , Wen Li
IPC分类号： H03M9/00
CPC分类号： G11C7/1051 , G11C7/10 , G11C7/1012 , G11C2207/107 , H03M9/00
摘要： A data sort device for converting parallel data to serial data is disclosed and provided. The data sort device may include a plurality of switches for receiving parallel data, each of which are controlled by a respective control signal and configured to alternatingly transmit data bits received via first and second input terminals.
摘要翻译：公开并提供了用于将并行数据转换为串行数据的数据分类装置。数据分类装置可以包括用于接收并行数据的多个开关，每个开关由相应的控制信号控制，并被配置为交替地发送经由第一和第二输入端接收的数据位。

10. 发明授权

US07318167B2 DDR II write data capture calibration 失效
标题翻译： DDR II写入数据采集校准
公开(公告)号：US07318167B2
公开(公告)日：2008-01-08
申请号：US11640983
申请日：2006-12-19
申请人： Wen Li , Christopher K. Morzano
发明人： Wen Li , Christopher K. Morzano
IPC分类号： G06F1/04 , G06F12/00
CPC分类号： G11C7/1078 , G11C7/02 , G11C7/1006 , G11C7/1066 , G11C7/1087 , G11C7/1093 , G11C7/1096 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C11/4096 , G11C2207/107 , G11C2207/2254
摘要： A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., “1100,” is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined pattern and adjusts a delay applied to the data signal until the predetermined pattern is recognized. Then the delay is further adjusted until the predetermined pattern is no longer recognized indicating that an edge of the eye of the data is near a clocking edge of the clocking signal. The delay applied to the data signal is then further adjusted by a predetermined amount to position the clock edge near the center of the data eye.
摘要翻译：公开了一种用于校准数字电路的输入数据路径的校准电路。在数据路径上发送诸如“1100”的重复数据模式的简单串。数字电路使用时钟信号捕获数据，检查预定模式的数据信号，并调整施加到数据信号的延迟，直到识别出预定模式。然后进一步调整延迟直到不再识别预定模式，指示数据的眼睛的边缘接近时钟信号的时钟边缘。然后对数据信号施加的延迟进一步调整预定量，以将时钟边缘定位在数据眼睛的中心附近。

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