专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09348406B2 Apparatus and method for activating and shutting down enhanced modules within an activated pipeline stage based on performance requirements and module priority 有权
标题翻译：基于性能要求和模块优先级激活和关闭激活的流水线级中的增强模块的装置和方法
公开(公告)号：US09348406B2
公开(公告)日：2016-05-24
申请号：US13457011
申请日：2012-04-26
申请人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Hua Yong Wang , Huan Hao Zou
发明人： Wen Bo Shen , Peng Shao , Yu Li , Xiao Tao Chang , Yi Ge , Hua Yong Wang , Huan Hao Zou
IPC分类号： G06F1/32 , G06F9/30 , G06F11/30 , G06F9/38
CPC分类号： G06F1/3287 , G06F9/3867 , G06F9/3885 , G06F9/4818 , G06F11/30 , G06F13/18 , Y02D10/14
摘要： The present invention discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, the base pipeline stages being activated all the while, and the enhanced pipeline stages being activated or shutdown according to requirements for performance of a workload. The present invention further discloses a method of processing instructions in a pipeline-based central processing unit, wherein the pipeline is partitioned into base pipeline stages and enhanced pipeline stages according to functions, each pipeline stage being partitioned into a base module and at least one enhanced module, the base module being activated all the while, and the enhanced module being activated or shutdown according to requirements for performance of a workload.
摘要翻译：本发明公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分为基本流水线阶段和增强流水线阶段，基本流水线阶段同时被激活，增强的流水线阶段根据工作负载的性能要求被激活或关闭。本发明还公开了一种在基于流水线的中央处理单元中处理指令的方法，其中根据功能将流水线划分成基本流水线级和增强的流水线级，每个流水线级分为基模块和至少一增强型模块，基本模块一直被激活，并且增强模块根据工作负载的性能要求被激活或关闭。

2. 发明申请

US20090248984A1 METHOD AND DEVICE FOR PERFORMING COPY-ON-WRITE IN A PROCESSOR 审中-公开
标题翻译：用于在处理器中执行复写的方法和设备
公开(公告)号：US20090248984A1
公开(公告)日：2009-10-01
申请号：US12410325
申请日：2009-03-24
申请人： Xiao Wei Shen , Hua Yong Wang , Wen Bo Shen , Peng Shao
发明人： Xiao Wei Shen , Hua Yong Wang , Wen Bo Shen , Peng Shao
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0884 , G06F12/0811
摘要： There are disclosed a method and device for performing Copy-on-Write in a processor. The processor comprises: processor cores, L1 caches each of which is logically divided into a first L1 cache and a second L1 cache, and L2 caches. The first L1 cache is used for saving new data value, and the second L1 cache for saving old data value. The method can comprise the steps of: in response to a store operation from said processor core, judging whether a corresponding cache line in said L2 cache has been modified; if it is determined a corresponding L2 cache line in said L2 cache has not been modified, copying old data value in the corresponding L2 cache line to said second L1 cache, and writing new data value to the corresponding L2 cache line; and if it is determined a corresponding L2 cache line in said L2 cache has been modified, writing new data value to the corresponding L2 cache line directly.
摘要翻译：公开了一种用于在处理器中执行写时复制的方法和装置。处理器包括：处理器核心，L1高速缓存，其中每个高速缓存被逻辑地划分为第一L1高速缓存和第二L1高速缓存以及L2高速缓存。第一个L1缓存用于保存新数据值，第二个L1缓存用于保存旧数据值。该方法可以包括以下步骤：响应于来自所述处理器核心的存储操作，判断所述L2高速缓存中的相应高速缓存行是否已被修改; 如果确定所述L2高速缓存中的对应的L2高速缓存行尚未被修改，则将相应的L2高速缓存行中的旧数据值复制到所述第二L1高速缓存，并将新的数据值写入对应的L2高速缓存行; 并且如果确定了所述L2高速缓存中的对应的L2高速缓存行已被修改，则将新的数据值直接写入对应的L2高速缓存行。

3. 发明授权

US09424744B2 Method and apparatus for traffic management 有权
标题翻译：交通管理方法和装置
公开(公告)号：US09424744B2
公开(公告)日：2016-08-23
申请号：US13505165
申请日：2010-10-18
申请人： Wei Xiong Shang , Hua Yong Wang , Zhe Xiang , Chun Ying , Jin Z. Zhou , Yan Feng Zhu
发明人： Wei Xiong Shang , Hua Yong Wang , Zhe Xiang , Chun Ying , Jin Z. Zhou , Yan Feng Zhu
IPC分类号： G08G1/01 , H04W4/02 , H04W4/04
CPC分类号： G08G1/0104 , H04W4/026 , H04W4/029 , H04W4/046
摘要： A method for determining travel time of a vehicle on a road, wherein the vehicle is operable within a mobile communication network, comprising: collecting historical communication events of a mobile user in order to obtain travel samples, wherein the historical communication events indicate when the mobile user travelled along a monitored road; determining a cell handover sequence from the historical communication events; determining from the cell handover sequence, one of more road segments of the monitored road; determining the travel time of the one or more road segments according to the travel time samples; selecting, for an undetermined road segment of the monitored road for which the real-time travel time is not determined from the collected historical communication events, a candidate mobile user that is most likely to appear on the undetermined road segment; actively positioning the candidate mobile user to obtain positioning information; and returning to the step of collecting communication events of a mobile user currently on a monitored road with the active positioning as one communication event for the candidate mobile user, to determine the real-time travel time of the undetermined road segment.
摘要翻译：一种用于确定车辆在道路上的行驶时间的方法，其中所述车辆在移动通信网络内可操作，包括：收集移动用户的历史通信事件以获得旅行样本，其中所述历史通信事件指示所述移动用户沿着监控的道路行驶; 从所述历史通信事件确定小区切换序列; 从所述小区切换序列确定所监视的道路的更多路段之一; 根据行驶时间样本确定一个或多个路段的行驶时间; 从所收集的历史通信事件中选择未确定实时旅行时间的被监测道路的未确定路段，最可能出现在未确定路段上的候选移动用户; 积极定位候选移动用户获取定位信息; 并且返回到采用主动定位的当前在被监视道路上的移动用户的通信事件作为候选移动用户的一个通信事件的步骤，以确定不确定路段的实时行进时间。

4. 发明授权

US08301864B2 Apparatus and method for executing rapid memory management unit emulation and full-system simulator 有权
标题翻译：用于执行快速存储器管理单元仿真和全系统仿真器的装置和方法
公开(公告)号：US08301864B2
公开(公告)日：2012-10-30
申请号：US12030163
申请日：2008-02-12
申请人： Hua Yong Wang , Kun Wang , Honesty Young
发明人： Hua Yong Wang , Kun Wang , Honesty Young
IPC分类号： G06F12/00
CPC分类号： G06F9/45504 , G06F9/45537 , G06F12/1027
摘要： A method for performing rapid memory management unit emulation of a computer program in a computer system, wherein address injection space of predefined size is allocated in the computer system and a virtual page number and a corresponding physical page number are stored in said address injection space, said method comprising steps of: comparing the virtual page number of the virtual address of a load/store instruction in a code segment in said computer program with the virtual address page number stored in said address injection space; if the two virtual page numbers are the same, then obtaining the corresponding physical address according to the physical page number stored in said address injection space; otherwise, performing address translation lookaside buffer search, that is, TLB search to obtain the corresponding physical address; and reading/writing data from/to said obtained corresponding physical address. The present invention also provides an apparatus and computer program product for implementing the method described above.
摘要翻译：一种用于在计算机系统中执行计算机程序的快速存储器管理单元仿真的方法，其中预定义大小的地址注入空间被分配在计算机系统中，并且虚拟页码和对应的物理页号存储在所述地址注入空间中，所述方法包括以下步骤：将所述计算机程序中的代码段中的加载/存储指令的虚拟地址的虚拟页面号码与存储在所述地址注入空间中的虚拟地址页码进行比较; 如果两个虚拟页码相同，则根据存储在所述地址注入空间中的物理页码获得对应的物理地址; 否则，执行地址转换后备缓冲区搜索，即TLB搜索获取相应的物理地址; 以及从所述获得的对应物理地址读取/写入数据。本发明还提供一种用于实现上述方法的装置和计算机程序产品。

5. 发明申请

US20100293534A1 USE OF VECTORIZATION INSTRUCTION SETS 有权
标题翻译：使用指令集
公开(公告)号：US20100293534A1
公开(公告)日：2010-11-18
申请号：US12466980
申请日：2009-05-15
申请人： HENRIQUE ANDRADE , Bugra Gedik , Hua Yong Wang , Kun-Lung Wu
发明人： HENRIQUE ANDRADE , Bugra Gedik , Hua Yong Wang , Kun-Lung Wu
IPC分类号： G06F9/45 , G06F15/76 , G06F9/06
CPC分类号： G06F8/447
摘要： In one embodiment, the invention is a method and apparatus for use of vectorization instruction sets. One embodiment of a method for generating vector instructions includes receiving source code written in a high-level programming language, wherein the source code includes at least one high-level instruction that performs multiple operations on a plurality of vector operands, and compiling the high-level instruction(s) into one or more low-level instructions, wherein the low-level instructions are in an instruction set of a specific computer architecture.
摘要翻译：在一个实施例中，本发明是用于矢量化指令集的方法和装置。用于产生矢量指令的方法的一个实施例包括接收以高级编程语言编写的源代码，其中源代码包括对多个向量操作数执行多个操作的至少一个高级指令，电平指令转换成一个或多个低级指令，其中低级指令位于特定计算机体系结构的指令集中。

6. 发明申请

US20090119089A1 METHOD, APPARATUS AND FULL-SYSTEM SIMULATOR FOR SPEEDING MMU SIMULATION 失效
标题翻译：用于加速MMU模拟的方法，装置和全系统模拟器
公开(公告)号：US20090119089A1
公开(公告)日：2009-05-07
申请号：US12259891
申请日：2008-10-28
申请人： Ahmed Gheith , Hua Yong Wang , Kun Wang , Yu Zhang
发明人： Ahmed Gheith , Hua Yong Wang , Kun Wang , Yu Zhang
IPC分类号： G06F9/455
CPC分类号： G06F9/45537 , G06F12/0223 , G06F12/1036 , G06F12/109 , G06F2212/151
摘要： A method, apparatus, and full-system simulator for speeding memory management unit simulation with direct address mapping on a host system, the host system supporting a full-system simulator, on which a guest system is simulated, the method comprising the following steps: setting a border in the logical space assigned for the full-system simulator by the host system, thereby dividing the logical space into a safe region and a simulator occupying region; shifting the full-system simulator itself from the occupied original host logical space to the simulator occupying region; and reserving the safe region for use with at least part of the guest system.
摘要翻译：一种用于通过主机系统上的直接地址映射来加速存储器管理单元仿真的方法，装置和全系统模拟器，所述主机系统支持模拟客机系统的全系统模拟器，所述方法包括以下步骤：在由主机系统分配给全系统模拟器的逻辑空间中设置边界，从而将逻辑空间划分为安全区域和模拟器占用区域; 将全系统仿真器本身从占用的原始主机逻辑空间转移到模拟器占用区域; 并保留与客户系统的至少一部分一起使用的安全区域。

7. 发明授权

US09047114B2 Method and system for analyzing parallelism of program code 有权
标题翻译：分析程序代码并行性的方法和系统
公开(公告)号：US09047114B2
公开(公告)日：2015-06-02
申请号：US13613572
申请日：2012-09-13
申请人： Bo Feng , Rong Yan , Kun Wang , Hua Yong Wang
发明人： Bo Feng , Rong Yan , Kun Wang , Hua Yong Wang
IPC分类号： G06F11/34 , G06F9/45
CPC分类号： G06F8/456
摘要： Methods and systems are provided for analyzing parallelism of program code. According to a method, the sequential execution of the program code is simulated so as to trace the execution procedure of the program code, and parallelism of the program code is analyzed based on the result of the trace to the execution procedure of the program code. Execution information of the program code is collected by simulating the sequential execution of the program code, and parallelism of the program code is analyzed based on the collected execution information, so as to allow programmers to perform parallel task partitioning of the program code with respect to a multi-core architecture more effectively, thus increasing the efficiency of parallel software development.
摘要翻译：提供了方法和系统来分析程序代码的并行性。根据一种方法，模拟程序代码的顺序执行，以便跟踪程序代码的执行过程，并根据对程序代码的执行过程的跟踪结果来分析程序代码的并行性。通过模拟程序代码的顺序执行来收集程序代码的执行信息，并且基于所收集的执行信息来分析程序代码的并行性，以便程序员能够相对于程序代码执行程序代码的并行任务划分多核架构更有效，从而提高并行软件开发的效率。

8. 发明授权

US08255201B2 Full-system ISA emulating system and process recognition method 失效
标题翻译：全系统ISA仿真系统和过程识别方法
公开(公告)号：US08255201B2
公开(公告)日：2012-08-28
申请号：US12107835
申请日：2008-04-23
申请人： Hua Yong Wang , Kun Wang , Honesty Young
发明人： Hua Yong Wang , Kun Wang , Honesty Young
IPC分类号： G06F9/455
CPC分类号： G06F9/45537
摘要： Disclosed is a method of recognizing a process in a full-system Instruction Set Architecture (ISA) emulator, comprising the steps of: recognizing a process based on a base address of a page table thereof, recognizing the switch between the processes when said base address of the page table has changed, recognizing the termination of a recorded process when the base address of the page table of the process which tries to modify the page table is not equal to the base address of the page table of the recorded process in the page table. With the recognized process, the binary translation results indexed based on content can be saved into a corresponding process repository, thereby achieving the permanent saving of the translation results and the reuse of translation and optimization on the basis of a previously executed program. Consequently, the overall performance of the full-system Industry Standard Architecture emulator is enhanced.
摘要翻译：公开了一种识别全系统指令集架构（ISA）仿真器中的处理的方法，包括以下步骤：基于其页表的基地址来识别进程，识别当所述基地址页面表已经改变，当尝试修改页表的处理的页表的基地址不等于页中记录的进程的页表的基地址时，识别记录处理的终止表。通过认可的过程，基于内容索引的二进制翻译结果可以保存到相应的处理库中，从而基于先前执行的程序实现翻译结果的永久保存和翻译和优化的重用。因此，全系统行业标准架构仿真器的整体性能得到提升。

9. 发明授权

US08140828B2 Handling transaction buffer overflow in multiprocessor by re-executing after waiting for peer processors to complete pending transactions and bypassing the buffer 有权
标题翻译：在等待对等体处理器完成未决事务并绕过缓冲区之后，通过重新执行来处理多处理器中的事务缓冲区溢出
公开(公告)号：US08140828B2
公开(公告)日：2012-03-20
申请号：US12325866
申请日：2008-12-01
申请人： Xiaowei Shen , Hua Yong Wang , Kun Wang
发明人： Xiaowei Shen , Hua Yong Wang , Kun Wang
IPC分类号： G06F15/163
CPC分类号： G06F9/466 , G06F9/526 , G06F12/0815 , G06F12/0842 , G06F12/0893
摘要： There is disclosed a method and apparatus for handling transaction buffer overflow in a multi-processor system as well as a transaction memory system in a multi-processor system. The method comprises the steps of: when overflow occurs in a transaction buffer of one processor, disabling peer processors from entering transactions, and waiting for any processor having a current transaction to complete its current transaction; re-executing the transaction resulting in the transaction buffer overflow without using the transaction buffer; and when the transaction execution is completed, enabling the peer processors for entering transactions.
摘要翻译：公开了一种在多处理器系统中处理事务缓冲器溢出以及多处理器系统中的事务存储器系统的方法和装置。该方法包括以下步骤：当在一个处理器的事务缓冲器中发生溢出时，禁止对等处理器进入事务，并等待具有当前事务的任何处理器完成其当前事务; 重新执行事务导致事务缓冲区溢出而不使用事务缓冲区; 并且当事务执行完成时，使对等体处理器能够进行事务处理。

10. 发明申请

US20090144524A1 Method and System for Handling Transaction Buffer Overflow In A Multiprocessor System 有权
标题翻译：在多处理器系统中处理事务缓冲区溢出的方法和系统
公开(公告)号：US20090144524A1
公开(公告)日：2009-06-04
申请号：US12325866
申请日：2008-12-01
申请人： Xiaowei Shen , Hua Yong Wang , Kun Wang
发明人： Xiaowei Shen , Hua Yong Wang , Kun Wang
IPC分类号： G06F15/76 , G06F9/06
CPC分类号： G06F9/466 , G06F9/526 , G06F12/0815 , G06F12/0842 , G06F12/0893
摘要： There is disclosed a method and apparatus for handling transaction buffer overflow in a multi-processor system as well as a transaction memory system in a multi-processor system. The method comprises the steps of: when overflow occurs in a transaction buffer of one processor, disabling peer processors from entering transactions, and waiting for any processor having a current transaction to complete its current transaction; re-executing the transaction resulting in the transaction buffer overflow without using the transaction buffer; and when the transaction execution is completed, enabling the peer processors for entering transactions.
摘要翻译：公开了一种在多处理器系统中处理事务缓冲器溢出以及多处理器系统中的事务存储器系统的方法和装置。该方法包括以下步骤：当在一个处理器的事务缓冲器中发生溢出时，禁止对等处理器进入事务，并等待具有当前事务的任何处理器完成其当前事务; 重新执行事务导致事务缓冲区溢出而不使用事务缓冲区; 并且当事务执行完成时，使对等体处理器能够进行事务处理。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式