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1. 发明授权

US07119444B2 Versatile system for charge dissipation in the formation of semiconductor device structures 有权
标题翻译：用于形成半导体器件结构的电荷耗散的通用系统
公开(公告)号：US07119444B2
公开(公告)日：2006-10-10
申请号：US10917763
申请日：2004-08-13
申请人： Weidong Tian , Bradley Sucher , Zafar Imam
发明人： Weidong Tian , Bradley Sucher , Zafar Imam
IPC分类号： H01L23/48
CPC分类号： H01L27/0248 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.
摘要翻译：本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏。衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。

2. 发明授权

US07592252B2 Versatile system for charge dissipation in the formation of semiconductor device structures 有权
标题翻译：用于形成半导体器件结构的电荷耗散的通用系统
公开(公告)号：US07592252B2
公开(公告)日：2009-09-22
申请号：US11468648
申请日：2006-08-30
申请人： Weidong Tian , Bradley Sucher , Zafar Imam
发明人： Weidong Tian , Bradley Sucher , Zafar Imam
IPC分类号： H01L21/4763
CPC分类号： H01L27/0248 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.
摘要翻译：本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏。衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。

3. 发明授权

US07671445B2 Versatile system for charge dissipation in the formation of semiconductor device structures 有权
标题翻译：用于形成半导体器件结构的电荷耗散的通用系统
公开(公告)号：US07671445B2
公开(公告)日：2010-03-02
申请号：US11420922
申请日：2006-05-30
申请人： Weidong Tian , Bradley Sucher , Zafar Imam
发明人： Weidong Tian , Bradley Sucher , Zafar Imam
IPC分类号： H01L23/60 , H01L23/48
CPC分类号： H01L27/0248 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.
摘要翻译：本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏。衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。

4. 发明申请

US20070057247A1 VERSATILE SYSTEM FOR CHARGE DISSIPATION IN THE FORMATION OF SEMICONDUCTOR DEVICE STRUCTURES 有权
标题翻译：用于形成半导体器件结构的充电放电的多元系统
公开(公告)号：US20070057247A1
公开(公告)日：2007-03-15
申请号：US11468648
申请日：2006-08-30
申请人： Weidong Tian , Bradley Sucher , Zafar Imam
发明人： Weidong Tian , Bradley Sucher , Zafar Imam
IPC分类号： H01L31/00
CPC分类号： H01L27/0248 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.
摘要翻译：本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏。衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。

5. 发明申请

US20060214170A1 VERSATILE SYSTEM FOR CHARGE DISSIPATION IN THE FORMATION OF SEMICONDUCTOR DEVICE STRUCTURES 有权
标题翻译：用于形成半导体器件结构的充电放电的多元系统
公开(公告)号：US20060214170A1
公开(公告)日：2006-09-28
申请号：US11420922
申请日：2006-05-30
申请人： Weidong Tian , Bradley Sucher , Zafar Imam
发明人： Weidong Tian , Bradley Sucher , Zafar Imam
IPC分类号： H01L29/76
CPC分类号： H01L27/0248 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.
摘要翻译：本发明提供了一种用于消散在制造半导体器件段（200）期间可能累积的任何异常电荷的系统，消除过应力或分解对可能由于异常电荷的不受控耗散而导致的焦点设备结构（208）的损坏。衬底（202）具有设置在衬底顶部的第一和第二中间结构（204,206），其中焦点结构设置在衬底之上。第一导电结构（210）设置在第二中间结构，焦点结构和第一中间结构的一部分的顶部。第三中间结构（214）在第一导电结构和第一中间层的上方相邻地设置。在器件段的周边区域（218）中通过第一和第三中间层向下形成空隙（216）。第二导电结构（220）设置在第三中间结构的顶部，使得其通过空隙连接衬底。

6. 发明申请

US20060033173A1 Versatile system for charge dissipation in the formation of semiconductor device structures 有权
公开(公告)号：US20060033173A1
公开(公告)日：2006-02-16
申请号：US10917763
申请日：2004-08-13
申请人： Weidong Tian , Bradley Sucher , Zafar Imam
发明人： Weidong Tian , Bradley Sucher , Zafar Imam
IPC分类号： H01L29/76 , H01L31/062
CPC分类号： H01L27/0248 , H01L23/62 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a system for dissipating any aberrant charge that may accumulate during the fabrication of a semiconductor device segment (200), obviating overstress or break down damage to a focal device structure (208) that might result from uncontrolled dissipation of the aberrant charge. A substrate (202) has first and second intermediate structures (204, 206) disposed atop the substrate, with the focal structure disposed atop the substrate therebetween. A first conductive structure (210) is disposed atop the second intermediate structure, the focal structure, and a portion of the first intermediate structure. A third intermediate structure (214) is disposed contiguously atop the first conductive structure and the first intermediate layer. A void (216) is formed in a peripheral region (218) of device segment, through the first and third intermediate layers down to the substrate. A second conductive structure (220) is disposed atop the third intermediate structure such that it couples the substrate through the void.

7. 发明申请

US20050136579A1 Method for manufacturing a metal oxide transistor having reduced 1/f noise 有权
标题翻译：制造具有降低的1 / f噪声的金属氧化物晶体管的方法
公开(公告)号：US20050136579A1
公开(公告)日：2005-06-23
申请号：US10744549
申请日：2003-12-22
申请人： Pinghai Hao , Larry Anderson , Fan Chi Hou , Xiaoju Wu , Yvonne Patton , Shanjen Pan , Zafar Imam
发明人： Pinghai Hao , Larry Anderson , Fan Chi Hou , Xiaoju Wu , Yvonne Patton , Shanjen Pan , Zafar Imam
IPC分类号： H01L21/265 , H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/28176 , H01L21/265 , H01L21/28035 , H01L21/28061 , H01L21/823857 , H01L29/7833
摘要： The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The method further includes implanting a fluorine dopant (130) into the polysilicon layer (115) at an implant dose of at least about 4×1014 atoms/cm2. The polysilicon layer (115) is thermally annealed such that a portion of the fluorine dopant (130) is diffused into the oxide layer (110) to thereby reduce a 1/f noise of the MOS device (100). Other embodiments of the provide a MOS device (300) manufactured by the above-described method and a method of manufacturing an integrated circuit (500) that includes the above-described method.
摘要翻译：本发明在一个实施例中提供一种降低金属氧化物半导体（MOS）器件（100）中的1 / f噪声的方法。该方法包括在硅衬底（105）上形成氧化物层（110）并在氧化物层（110）上沉积多晶硅层（115）。该方法还包括以至少约4×10 14原子/ cm 2的注入剂量将氟掺杂剂（130）注入到多晶硅层（115）中。多晶硅层（115）被热退火，使得氟掺杂剂（130）的一部分扩散到氧化物层（110）中，从而降低MOS器件（100）的1 / f噪声。提供通过上述方法制造的MOS器件（300）和包括上述方法的集成电路（500）的制造方法的其它实施例。

8. 发明授权

US07018880B2 Method for manufacturing a MOS transistor having reduced 1/f noise 有权
标题翻译：制造具有降低的1 / f噪声的MOS晶体管的方法
公开(公告)号：US07018880B2
公开(公告)日：2006-03-28
申请号：US10744549
申请日：2003-12-22
申请人： Pinghai Hao , Larry B. Anderson , Fan Chi Hou , Xiaoju Wu , Yvonne Patton , Shanjen Pan , Zafar Imam
发明人： Pinghai Hao , Larry B. Anderson , Fan Chi Hou , Xiaoju Wu , Yvonne Patton , Shanjen Pan , Zafar Imam
IPC分类号： H01L21/336 , H01L21/8234
CPC分类号： H01L21/28176 , H01L21/265 , H01L21/28035 , H01L21/28061 , H01L21/823857 , H01L29/7833
摘要： The present invention provides, in one embodiment, a method of reducing 1/f noise in a metal oxide semiconductor (MOS) device (100). The method comprises forming an oxide layer (110) on a silicon substrate (105) and depositing a polysilicon layer (115) on the oxide layer (110). The method further includes implanting a fluorine dopant (130) into the polysilicon layer (115) at an implant dose of at least about 4×1014 atoms/cm2. The polysilicon layer (115) is thermally annealed such that a portion of the fluorine dopant (130) is diffused into the oxide layer (110) to thereby reduce a 1/f noise of the MOS device (100). Other embodiments of the provide a MOS device (300) manufactured by the above-described method and a method of manufacturing an integrated circuit (500) that includes the above-described method.
摘要翻译：本发明在一个实施例中提供一种降低金属氧化物半导体（MOS）器件（100）中的1 / f噪声的方法。该方法包括在硅衬底（105）上形成氧化物层（110）并在氧化物层（110）上沉积多晶硅层（115）。该方法还包括以至少约4×10 14原子/ cm 2的注入剂量将氟掺杂剂（130）注入到多晶硅层（115）中。多晶硅层（115）被热退火，使得氟掺杂剂（130）的一部分扩散到氧化物层（110）中，从而降低MOS器件（100）的1 / f噪声。提供通过上述方法制造的MOS器件（300）和包括上述方法的集成电路（500）的制造方法的其它实施例。

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