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1. 发明授权

US5479121A Compensating circuit for MOSFET analog switches 失效
标题翻译： MOSFET模拟开关补偿电路
公开(公告)号：US5479121A
公开(公告)日：1995-12-26
申请号：US394771
申请日：1995-02-27
申请人： Wei-Chen Shen , Yen-Bin Gu , Chu-Chang Lin , Ming-Jer Chen , Po-Chin Hsu , Tien-Yu Wu
发明人： Wei-Chen Shen , Yen-Bin Gu , Chu-Chang Lin , Ming-Jer Chen , Po-Chin Hsu , Tien-Yu Wu
IPC分类号： G11C27/02
CPC分类号： G11C27/026
摘要： This invention deals with the problem of an error voltage in a MOSFET analog switch sample and hold circuit caused by the turn off charge in the MOSFET analog switch. The invention provides a compensating circuit which can be adjusted to exactly compensate for the turn off charge which causes the error so that the error can be reduced to zero or nearly zero. The compensating circuit can be used in both open loop and closed loop sample and hold circuits. The compensating circuit can be used in combination with a Miller feedback circuit for eliminating the error voltage.
摘要翻译：本发明涉及由MOSFET模拟开关中的关断电荷引起的MOSFET模拟开关采样和保持电路中的误差电压的问题。本发明提供一种补偿电路，其可被调整以精确地补偿导致误差的关断电荷，使得误差可以降低到零或接近零。补偿电路可用于开环和闭环采样保持电路。补偿电路可以与米勒反馈电路组合使用，以消除误差电压。

2. 发明授权

US07084792B2 Circuit for zero offset auto-calibration and method thereof 失效
标题翻译：零偏自动校准电路及其方法
公开(公告)号：US07084792B2
公开(公告)日：2006-08-01
申请号：US11161172
申请日：2005-07-26
申请人： Po-Chin Hsu
发明人： Po-Chin Hsu
IPC分类号： H03M1/06
CPC分类号： H03M1/1023
摘要： A circuit for zero offset auto-calibration and a method thereof suitable for video signal analog-to-digital converters are provided. The circuit is connected between the last stage of a pipeline analog-to-digital converter (the pipeline ADC) and a differential signal buffer, comprised of an indicator signal generator, a calibration voltage generator and a timing controller. The indicator signal generator outputs an indicator signal to indicate whether the output from the pipeline ADC is too high or too low. The calibration voltage generator provides the differential signal buffer with a calibration voltage and, within a calibration period determined by a delay signal, regulates the calibration voltage in response to the indicator signal. The timing controller outputs the delay signal to control the length of the calibration period, so that the compensation speed of the pipeline ADC is less than its converting delay speed, and the compensation loop gets stable.
摘要翻译：提供了一种用于零偏移自动校准的电路及其适用于视频信号模拟 - 数字转换器的方法。电路连接在流水线模数转换器（流水线ADC）的最后一级和由指示信号发生器，校准电压发生器和定时控制器组成的差分信号缓冲器之间。指示信号发生器输出一个指示信号，以指示流水线ADC的输出是否过高或过低。校准电压发生器为差分信号缓冲器提供校准电压，并且在由延迟信号确定的校准周期内，响应于指示信号来调节校准电压。定时控制器输出延迟信号来控制校准周期的长度，使得流水线ADC的补偿速度小于其转换延迟速度，补偿回路稳定。

3. 发明授权

US5726653A Tri-step analog-to-digital converter 失效
标题翻译：三步模数转换器
公开(公告)号：US5726653A
公开(公告)日：1998-03-10
申请号：US589277
申请日：1996-01-22
申请人： Po-Chin Hsu , Yung-Yu Lin
发明人： Po-Chin Hsu , Yung-Yu Lin
IPC分类号： H03M1/14 , H03M1/36 , H03M1/12
CPC分类号： H03M1/144 , H03M1/365
摘要： An analog to digital converter for the conversion of an analog input signal to a digital output code is disclosed. The analog to digital converter has a voltage reference generator to create a plurality of voltage references that divides the total conversion range of the input into increments equal to the smallest resolution increment. The digital output code is divided into most significant bits, intermediate significant bits and least significant bits. The most significant bits are encoded from a set of coarse digital signals that are formed in a set of coarse comparators. The coarse digital code is used to determine the selection of the sub-coarse voltage references. The intermediate significant bits are encoded from a set of subcoarse digital signals. The subcoarse digital code that and the coarse digital code are used to determine the selection of the fine voltage references. The least significant bits and a correction factor for the intermediate significant bits are encoded from a set of fine digital signals. The digital codes that form the most significant bits, the intermediate bits, the fine bits, and the correction factor are encoded in an output encoder to form the digital output word.
摘要翻译：公开了一种用于将模拟输入信号转换为数字输出代码的模数转换器。模数转换器具有一个电压参考发生器，以产生将输入的总转换范围分成等于最小分辨率增量的增量的多个电压基准。数字输出代码被分为最高有效位，中间有效位和最低有效位。最高有效位是从一组粗略比较器中形成的一组粗略数字信号进行编码的。粗略的数字码用于确定子粗略参考电压的选择。中间有效位由一组次数数字信号编码。用于确定精细电压基准的选择的粗略数字代码和粗略数字代码。中间有效位的最低有效位和校正因子由一组精细数字信号编码。形成最高有效位的数字代码，中间位，精细位和校正因子被编码在输出编码器中以形成数字输出字。

4. 发明授权

US5631650A Sample/hold free most significant bit comparator using bisection comparators 失效
标题翻译：采样/保持最高有效位比较器使用二分比较器
公开(公告)号：US5631650A
公开(公告)日：1997-05-20
申请号：US405721
申请日：1995-03-17
申请人： Po-Chin Hsu
发明人： Po-Chin Hsu
IPC分类号： H03M1/14 , H03M1/36 , H03M1/42
CPC分类号： H03M1/145 , H03M1/365
摘要： This invention provides an analog to digital converter using bisection comparators to determine the Most Significant Bits of the input voltage. The bisection comparator is comprised of three inverting amplifiers and does not use an auto zero phase, which reduces the power dissipation in the bisection comparator significantly. The bisection comparator does not use a sample and hold circuit and no capacitors are required, which significantly reduces the size of the integrated circuit chip. The analog to digital converter uses a number of bisection comparators to determine the Most Significant Bits of the input voltage and fine analog to digital converters to determine the Least Significant Bits of the input voltage. The outputs of the bisection comparators are used to set the switches of the fine analog to digital converters.
摘要翻译：本发明提供了一种使用二分比较器来确定输入电压的最高有效位的模数转换器。二等分比较器由三个反相放大器组成，不使用自动零相位，这显着降低了二分比较器中的功耗。二等分比较器不使用采样和保持电路，并且不需要电容器，这大大减小了集成电路芯片的尺寸。模数转换器使用多个二分比较器来确定输入电压的最高有效位和精细的模数转换器，以确定输入电压的最低有效位。二等分比较器的输出用于设置精细模数转换器的开关。

5. 发明授权

US5581255A Embedded subranging analog to digital converter 失效
标题翻译：嵌入式子模拟数字转换器
公开(公告)号：US5581255A
公开(公告)日：1996-12-03
申请号：US497881
申请日：1995-07-03
申请人： Po-Chin Hsu
发明人： Po-Chin Hsu
IPC分类号： H03M1/14 , H03M1/36 , H03M1/16
CPC分类号： H03M1/147 , H03M1/365
摘要： An analog to digital converter for the conversion of an analog input voltage to a digital output voltage signal of n bits has a plurality of voltage sources (Voltage Reference Generator) that divide the total range of voltage of the conversion input into increments of voltage equal to the smallest increment of resolution. The n bits of digital output are divided into an upper segment or Most Significant Bits (MSB) and a lower segment or Least Significant Bits (LSB). The Most Significant bits are encoded from a set of digital signals from a plurality of comparators (Coarse Subrange Comparators) that compare the voltage input with a subset of Voltage Reference Generator representing the coarse range. The Coarse Subrange Comparator outputs are used to determine the placement of a plurality of Embedded Subrange Comparators that are used to detect any error in the codes of the Coarse Subrange Comparators. The output of the Coarse and Embedded Subrange Comparators are now used to determine the connection of a plurality of Fine Subrange Comparators to the Voltage Reference Generator in the section of the Coarse Subrange to accurately determine the smallest increment of resolution for the Analog to Digital Converter. The codes from the Coarse, Embedded, and Fine Subrange Comparators become the input to an encoder to determine the output digital voltage that represent the input voltage.
摘要翻译：用于将模拟输入电压转换为n位数字输出电压信号的模数转换器具有多个电压源（电压基准发生器），其将转换输入的电压的总范围除以等于分辨率最小的增量。数字输出的n位被分为上段或最高有效位（MSB）和下段或最低有效位（LSB）。最高有效位由来自多个比较器（粗略子范围比较器）的一组数字信号进行编码，该比较器将电压输入与表示粗略范围的电压参考发生器的子集进行比较。粗略子比较器输出用于确定用于检测粗略子范围比较器的代码中的任何错误的多个嵌入式子范围比较器的位置。粗调和嵌入式子范围比较器的输出现在用于确定多个精细子范围比较器与粗略子范围部分中的参考电压发生器的连接，以精确确定模数转换器的最小分辨率增量。粗调，嵌入和精细子范围比较器的代码成为编码器的输入，用于确定表示输入电压的输出数字电压。

6. 发明申请

US20060109151A1 CIRCUIT FOR ZERO OFFSET AUTO-CALIBRATION AND METHOD THEREOF 失效
标题翻译：用于零偏置自动校准的电路及其方法
公开(公告)号：US20060109151A1
公开(公告)日：2006-05-25
申请号：US11161172
申请日：2005-07-26
申请人： Po-Chin Hsu
发明人： Po-Chin Hsu
IPC分类号： H03M1/10
CPC分类号： H03M1/1023
摘要： A circuit for zero offset auto-calibration and a method thereof suitable for video signal analog-to-digital converters are provided. The circuit is connected between the last stage of a pipeline analog-to-digital converter (the pipeline ADC) and a differential signal buffer, comprised of an indicator signal generator, a calibration voltage generator and a timing controller. The indicator signal generator outputs an indicator signal to indicate whether the output from the pipeline ADC is too high or too low. The calibration voltage generator provides the differential signal buffer with a calibration voltage and, within a calibration period determined by a delay signal, regulates the calibration voltage in response to the indicator signal. The timing controller outputs the delay signal to control the length of the calibration period, so that the compensation speed of the pipeline ADC is less than its converting delay speed, and the compensation loop gets stable.
摘要翻译：提供了一种用于零偏移自动校准的电路及其适用于视频信号模拟 - 数字转换器的方法。电路连接在流水线模数转换器（流水线ADC）的最后一级和由指示信号发生器，校准电压发生器和定时控制器组成的差分信号缓冲器之间。指示信号发生器输出一个指示信号，以指示流水线ADC的输出是否过高或过低。校准电压发生器为差分信号缓冲器提供校准电压，并且在由延迟信号确定的校准周期内，响应于指示信号来调节校准电压。定时控制器输出延迟信号来控制校准周期的长度，使得流水线ADC的补偿速度小于其转换延迟速度，补偿回路稳定。

7. 发明申请

US20060109037A1 POWER-ON RESET CIRCUIT 有权
标题翻译：上电复位电路
公开(公告)号：US20060109037A1
公开(公告)日：2006-05-25
申请号：US11161260
申请日：2005-07-28
申请人： Po-Chin Hsu
发明人： Po-Chin Hsu
IPC分类号： H03L7/00
CPC分类号： H03K17/302 , H03K17/223
摘要： A power-on reset circuit is provided. The power-on reset circuit includes an adjusting circuit, a charging/discharging unit and an output circuit. The adjusting circuit receives and adjusts a clock signal so as to output a control signal, wherein a minimum level of the control signal is clamped to be higher than a pre-defined level. The charging/discharging unit having a capacitor apparatus receives the control signal, determines whether to charge/discharge the capacitor apparatus based on the control signal, and outputs a storage voltage of the capacitor apparatus. The output circuit receives the storage voltage and outputs the reset signal. Wherein, the adjusting circuit determines the charging/discharging duty cycle of the charging/discharging unit by adjusting the waveform and the minimum level of the control signal. The output circuit enables/disables the reset signal according to whether the storage voltage reaches the threshold voltage of the output circuit.
摘要翻译：提供上电复位电路。上电复位电路包括调整电路，充电/放电单元和输出电路。调整电路接收并调整时钟信号，以输出控制信号，其中控制信号的最小电平被钳位为高于预定电平。具有电容器装置的充电/放电单元接收控制信号，基于控制信号确定是否对电容器装置进行充电/放电，并输出电容器装置的存储电压。输出电路接收存储电压并输出复位信号。其中，调节电路通过调整控制信号的波形和最小电平来确定充放电单元的充电/放电占空比。根据存储电压是否达到输出电路的阈值电压，输出电路使能/禁止复位信号。

8. 发明授权

US07274227B2 Power-on reset circuit 有权
标题翻译：上电复位电路
公开(公告)号：US07274227B2
公开(公告)日：2007-09-25
申请号：US11161260
申请日：2005-07-28
申请人： Po-Chin Hsu
发明人： Po-Chin Hsu
IPC分类号： H03L7/00 , H03K3/02
CPC分类号： H03K17/302 , H03K17/223
摘要： A power-on reset circuit is provided. The power-on reset circuit includes an adjusting circuit, a charging/discharging unit and an output circuit. The adjusting circuit receives and adjusts a clock signal so as to output a control signal, wherein a minimum level of the control signal is clamped to be higher than a pre-defined level. The charging/discharging unit having a capacitor apparatus receives the control signal, determines whether to charge/discharge the capacitor apparatus based on the control signal, and outputs a storage voltage of the capacitor apparatus. The output circuit receives the storage voltage and outputs the reset signal. Wherein, the adjusting circuit determines the charging/discharging duty cycle of the charging/discharging unit by adjusting the waveform and the minimum level of the control signal. The output circuit enables/disables the reset signal according to whether the storage voltage reaches the threshold voltage of the output circuit.
摘要翻译：提供上电复位电路。上电复位电路包括调整电路，充电/放电单元和输出电路。调整电路接收并调整时钟信号，以输出控制信号，其中控制信号的最小电平被钳位为高于预定电平。具有电容器装置的充电/放电单元接收控制信号，基于控制信号确定是否对电容器装置进行充电/放电，并输出电容器装置的存储电压。输出电路接收存储电压并输出复位信号。其中，调节电路通过调整控制信号的波形和最小电平来确定充放电单元的充电/放电占空比。根据存储电压是否达到输出电路的阈值电压，输出电路使能/禁止复位信号。

9. 发明授权

US07164300B2 Power-low reset circuit 有权
标题翻译：电源低复位电路
公开(公告)号：US07164300B2
公开(公告)日：2007-01-16
申请号：US11161257
申请日：2005-07-28
申请人： Po-Chin Hsu
发明人： Po-Chin Hsu
IPC分类号： H03K3/02 , H03L7/00
CPC分类号： H03K17/223 , H03K17/302
摘要： A power-low reset circuit is provided. The power-low reset circuit receives a reset signal outputted from a power on reset circuit and a stored voltage of a capacitive device in the power-on reset circuit provides an electrical path when a power voltage drops under a predetermined voltage level. The power-on reset circuit is used for generating the reset signal at an initial moment of turning on a power source. The capacitive device can be discharged or charged through the electrical path to restore to its initial status.
摘要翻译：提供掉电复位电路。功率低复位电路接收从上电复位电路输出的复位信号，并且电源复位电路中的电容性器件的存储电压在电源电压下降到预定电压电平时提供电路径。上电复位电路用于在打开电源的初始时刻产生复位信号。电容器件可以通过电路放电或充电，以恢复其初始状态。

10. 发明申请

US20060109036A1 POWER-LOW RESET CIRCUIT 有权
标题翻译：低功耗复位电路
公开(公告)号：US20060109036A1
公开(公告)日：2006-05-25
申请号：US11161257
申请日：2005-07-28
申请人： Po-Chin Hsu
发明人： Po-Chin Hsu
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , H03K17/302
摘要： A power-low reset circuit is provided. The power-low reset circuit receives a reset signal outputted from a power on reset circuit and a stored voltage of a capacitive device in the power-on reset circuit provides an electrical path when a power voltage drops under a predetermined voltage level. The power-on reset circuit is used for generating the reset signal at an initial moment of turning on a power source. The capacitive device can be discharged or charged through the electrical path to restore to its initial status.
摘要翻译：提供掉电复位电路。功率低复位电路接收从上电复位电路输出的复位信号，并且电源复位电路中的电容性器件的存储电压在电压降低到预定电压电平时提供电路径。上电复位电路用于在打开电源的初始时刻产生复位信号。电容器件可以通过电气路径放电或充电，以恢复其初始状态。

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