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1. 发明申请

US20110007551A1 Non-Volatile Memory Cell with Non-Ohmic Selection Layer 有权
标题翻译：具有非欧姆选择层的非易失性存储单元
公开(公告)号：US20110007551A1
公开(公告)日：2011-01-13
申请号：US12502222
申请日：2009-07-13
申请人： Wei Tian , Insik Jin , Venugopalan Vaithyanathan , Haiwen Xi , Michael Xuefei Tang , Brian Lee
发明人： Wei Tian , Insik Jin , Venugopalan Vaithyanathan , Haiwen Xi , Michael Xuefei Tang , Brian Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/51 , G11C2213/76 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/1246
摘要： A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.
摘要翻译：公开了一种包括非欧姆选择层的非易失性存储单元和相关联的方法。根据一些实施例，非易失性存储器单元由耦合到非欧姆选择层的电阻感测元件（RSE）组成。响应于大于或等于预定阈值的电流，选择层被配置为从第一电阻状态转变到第二电阻状态。

2. 发明授权

US08203865B2 Non-volatile memory cell with non-ohmic selection layer 有权
标题翻译：具有非欧姆选择层的非易失性存储单元
公开(公告)号：US08203865B2
公开(公告)日：2012-06-19
申请号：US13087087
申请日：2011-04-14
申请人： Wei Tian , Insik Jin , Venugopalan Vaithyanathan , Haiwen Xi , Michael Xuefei Tang , Brian Lee
发明人： Wei Tian , Insik Jin , Venugopalan Vaithyanathan , Haiwen Xi , Michael Xuefei Tang , Brian Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/51 , G11C2213/76 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/1246
摘要： A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.
摘要翻译：公开了一种包括非欧姆选择层的非易失性存储单元和相关联的方法。根据一些实施例，非易失性存储器单元由耦合到非欧姆选择层的电阻感测元件（RSE）组成。响应于大于或等于预定阈值的电流，选择层被配置为从第一电阻状态转变到第二电阻状态。

3. 发明授权

US07936585B2 Non-volatile memory cell with non-ohmic selection layer 有权
标题翻译：具有非欧姆选择层的非易失性存储单元
公开(公告)号：US07936585B2
公开(公告)日：2011-05-03
申请号：US12502222
申请日：2009-07-13
申请人： Wei Tian , Insik Jin , Venugopalan Vaithyanathan , Haiwen Xi , Michael Xuefei Tang , Brian Lee
发明人： Wei Tian , Insik Jin , Venugopalan Vaithyanathan , Haiwen Xi , Michael Xuefei Tang , Brian Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/51 , G11C2213/76 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/1246
摘要： A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.
摘要翻译：公开了一种包括非欧姆选择层的非易失性存储单元和相关联的方法。根据一些实施例，非易失性存储器单元由耦合到非欧姆选择层的电阻感测元件（RSE）组成。响应于大于或等于预定阈值的电流，选择层被配置为从第一电阻状态转变到第二电阻状态。

4. 发明申请

US20110188293A1 Non-Volatile Memory Cell With Non-Ohmic Selection Layer 有权
标题翻译：非易失性存储单元与非欧姆选择层
公开(公告)号：US20110188293A1
公开(公告)日：2011-08-04
申请号：US13087087
申请日：2011-04-14
申请人： Wei Tian , Insik Jin , Venugopalan Vaithyanathan , Haiwen Xi , Michael Xuefei Tang , Brian Lee
发明人： Wei Tian , Insik Jin , Venugopalan Vaithyanathan , Haiwen Xi , Michael Xuefei Tang , Brian Lee
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C13/0011 , G11C13/003 , G11C13/0069 , G11C2013/0073 , G11C2213/51 , G11C2213/76 , H01L27/2409 , H01L45/085 , H01L45/1233 , H01L45/1246
摘要： A non-volatile memory cell and associated method is disclosed that includes a non-ohmic selection layer. In accordance with some embodiments, a non-volatile memory cell consists of a resistive sense element (RSE) coupled to a non-ohmic selection layer. The selection layer is configured to transition from a first resistive state to a second resistive state in response to a current greater than or equal to a predetermined threshold.
摘要翻译：公开了一种包括非欧姆选择层的非易失性存储单元和相关联的方法。根据一些实施例，非易失性存储器单元由耦合到非欧姆选择层的电阻感测元件（RSE）组成。响应于大于或等于预定阈值的电流，选择层被配置为从第一电阻状态转变到第二电阻状态。

5. 发明申请

US20100117051A1 MEMORY CELLS INCLUDING NANOPOROUS LAYERS CONTAINING CONDUCTIVE MATERIAL 失效
标题翻译：包含导电材料的纳米层的记忆细胞
公开(公告)号：US20100117051A1
公开(公告)日：2010-05-13
申请号：US12269507
申请日：2008-11-12
申请人： Wei Tian , Venkatram Venkatasamy , Ming Sun , Michael Xuefei Tang , Insik Jin , Dimitar V. Dimitrov
发明人： Wei Tian , Venkatram Venkatasamy , Ming Sun , Michael Xuefei Tang , Insik Jin , Dimitar V. Dimitrov
IPC分类号： H01L47/00 , H01L21/44
CPC分类号： H01L27/2472 , H01L21/76816 , H01L23/5226 , H01L27/228 , H01L27/2436 , H01L43/08 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1616 , H01L45/1625 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A memory cell that includes a first contact having a first surface and an opposing second surface; a second contact having a first surface and an opposing second surface; a memory material layer having a first surface and an opposing second surface; and a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer including at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal, wherein a surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the second surface of the nanoporous layer is in contact with a surface of the memory material layer.
摘要翻译：一种存储单元，包括具有第一表面和相对的第二表面的第一触点; 具有第一表面和相对的第二表面的第二触点; 存储材料层，其具有第一表面和相对的第二表面; 以及具有第一表面和相对的第二表面的纳米多孔层，所述纳米多孔层包括至少一个纳米孔和介电材料，所述至少一个纳米孔基本上填充有导电金属，其中所述纳米多孔层的表面与第一接触面或第二接触面的表面和纳米多孔层的第二表面与记忆材料层的表面接触。

6. 发明授权

US07750386B2 Memory cells including nanoporous layers containing conductive material 失效
标题翻译：记忆单元包括含有导电材料的纳米多孔层
公开(公告)号：US07750386B2
公开(公告)日：2010-07-06
申请号：US12269507
申请日：2008-11-12
申请人： Wei Tian , Venkatram Venkatasamy , Ming Sun , Michael Xuefei Tang , Insik Jin , Dimitar V. Dimitrov
发明人： Wei Tian , Venkatram Venkatasamy , Ming Sun , Michael Xuefei Tang , Insik Jin , Dimitar V. Dimitrov
IPC分类号： H01L29/76 , H01L21/8242
CPC分类号： H01L27/2472 , H01L21/76816 , H01L23/5226 , H01L27/228 , H01L27/2436 , H01L43/08 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1273 , H01L45/143 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1616 , H01L45/1625 , H01L2221/1047 , H01L2924/0002 , H01L2924/00
摘要： A memory cell that includes a first contact having a first surface and an opposing second surface; a second contact having a first surface and an opposing second surface; a memory material layer having a first surface and an opposing second surface; and a nanoporous layer having a first surface and an opposing second surface, the nanoporous layer including at least one nanopore and dielectric material, the at least one nanopore being substantially filled with a conductive metal, wherein a surface of the nanoporous layer is in contact with a surface of the first contact or the second contact and the second surface of the nanoporous layer is in contact with a surface of the memory material layer.
摘要翻译：一种存储单元，包括具有第一表面和相对的第二表面的第一触点; 具有第一表面和相对的第二表面的第二触点; 存储材料层，其具有第一表面和相对的第二表面; 以及具有第一表面和相对的第二表面的纳米多孔层，所述纳米多孔层包括至少一个纳米孔和介电材料，所述至少一个纳米孔基本上被导电金属填充，其中所述纳米多孔层的表面与第一接触面或第二接触面的表面和纳米多孔层的第二表面与记忆材料层的表面接触。

7. 发明申请

US20100108975A1 NON-VOLATILE MEMORY CELL FORMATION 审中-公开
标题翻译：非挥发性记忆细胞形成
公开(公告)号：US20100108975A1
公开(公告)日：2010-05-06
申请号：US12265551
申请日：2008-11-05
申请人： Ming Sun , Wei Tian , Insik Jin , Michael Xuefei Tang , Andrew James Wirebaugh
发明人： Ming Sun , Wei Tian , Insik Jin , Michael Xuefei Tang , Andrew James Wirebaugh
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , G11C13/0011 , G11C2213/51 , G11C2213/56 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/1266 , H01L45/141 , H01L45/142 , H01L45/144 , H01L45/1658
摘要： A method and apparatus for forming a non-volatile memory cell, such as a PMC memory cell. In some embodiments, a first electrode is connected to a source while a second electrode is connected to a ground. An ionic region is located between the first and second electrodes and comprises a doping layer, composite layer, and electrolyte layer. The composite layer has a low resistive state and the electrolyte layer switches from a high resistive state to a low resistive state based on the presence of a filament.
摘要翻译：一种用于形成诸如PMC存储单元的非易失性存储单元的方法和装置。在一些实施例中，第一电极连接到源，而第二电极连接到地。离子区位于第一和第二电极之间，并且包括掺杂层，复合层和电解质层。复合层具有低电阻状态，并且基于长丝的存在，电解质层从高电阻状态切换到低电阻状态。

8. 发明授权

US08466524B2 Static magnetic field assisted resistive sense element 有权
公开(公告)号：US08466524B2
公开(公告)日：2013-06-18
申请号：US13040155
申请日：2011-03-03
申请人： Yuankai Zheng , Xiaohua Lou , Haiwen Xi , Michael Xuefei Tang
发明人： Yuankai Zheng , Xiaohua Lou , Haiwen Xi , Michael Xuefei Tang
IPC分类号： H01L29/82 , G11C11/02
CPC分类号： H01L43/08 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： Apparatus and associated method for writing data to a non-volatile memory cell, such as spin-torque transfer random access memory (STRAM). In accordance with some embodiments, a resistive sense element (RSE) has a heat assist region, magnetic tunneling junction (MTJ), and pinned region. When a first logical state is written to the MTJ with a spin polarized current, the pinned and heat assist regions each have a substantially zero net magnetic moment. When a second logical state is written to the MTJ with a static magnetic field, the pinned region has a substantially zero net magnetic moment and the heat assist region has a non-zero net magnetic moment.

9. 发明授权

US08422278B2 Memory with separate read and write paths 有权
标题翻译：内存具有单独的读写路径
公开(公告)号：US08422278B2
公开(公告)日：2013-04-16
申请号：US12974679
申请日：2010-12-21
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/15
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switche the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。磁性隧道结数据单元电耦合在读取位线和读取源极线之间。磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。写入电流通过巨磁电阻单元，以在高电阻状态和低电阻状态之间切换巨磁电阻单元。磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

10. 发明授权

US08400823B2 Memory with separate read and write paths 有权
标题翻译：内存具有单独的读写路径
公开(公告)号：US08400823B2
公开(公告)日：2013-03-19
申请号：US12774016
申请日：2010-05-05
申请人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
发明人： Haiwen Xi , Hongyue Liu , Michael Xuefei Tang , Antoine Khoueir , Song S. Xue
IPC分类号： G11C11/00
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A memory unit includes a giant magnetoresistance cell electrically coupled between a write bit line and a write source line. The giant magnetoresistance cell includes a free magnetic layer separated from a first pinned magnetic layer by a first non-magnetic electrically conducting layer. A magnetic tunnel junction data cell is electrically coupled between a read bit line and a read source line. The magnetic tunnel junction data cell includes the free magnetic layer separated from a second pinned magnetic layer by an oxide barrier layer. A write current passes through the giant magnetoresistance cell to switch the giant magnetoresistance cell between a high resistance state and a low resistance state. The magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by magnetostatic coupling with the giant magnetoresistance cell, and be read by a read current passing though the magnetic tunnel junction data cell.
摘要翻译：存储单元包括电耦合在写位线和写入源线之间的巨磁电阻单元。巨磁阻单元包括通过第一非磁性导电层与第一固定磁性层分离的自由磁性层。磁性隧道结数据单元电耦合在读取位线和读取源极线之间。磁性隧道结数据单元包括通过氧化物阻挡层与第二固定磁性层分离的自由磁性层。写入电流通过巨磁电阻单元，以将巨磁阻单元切换到高电阻状态和低电阻状态之间。磁隧道结数据单元被配置为通过与巨磁电阻单元的静磁耦合在高电阻状态和低电阻状态之间切换，并且通过通过磁性隧道结数据单元的读取电流来读取。

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