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1. 发明授权

US08866122B1 Resistive switching devices having a buffer layer and methods of formation thereof 有权
标题翻译：具有缓冲层的电阻式开关器件及其形成方法
公开(公告)号：US08866122B1
公开(公告)日：2014-10-21
申请号：US13517653
申请日：2012-06-14
申请人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Kuei-Chang Tsai , Jeffrey Shields , Janet Wang
发明人： Wei Ti Lee , Chakravarthy Gopalan , Yi Ma , Kuei-Chang Tsai , Jeffrey Shields , Janet Wang
IPC分类号： H01L47/00
CPC分类号： H01L45/143 , H01L45/085 , H01L45/1233 , H01L45/1266 , H01L45/145 , H01L45/146 , H01L45/147 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： In one embodiment, a resistive switching device includes a bottom electrode, a switching layer, a buffer layer, and a top electrode. The switching layer is disposed over the bottom electrode. The buffer layer is disposed over the switching layer and provides a buffer of ions of a memory metal. The buffer layer includes an alloy of the memory metal with an alloying element, which includes antimony, tin, bismuth, aluminum, germanium, silicon, or arsenic. The top electrode is disposed over the buffer layer and provides a source of the memory metal.
摘要翻译：在一个实施例中，电阻式开关器件包括底部电极，开关层，缓冲层和顶部电极。开关层设置在底部电极上。缓冲层设置在开关层上并提供存储金属离子的缓冲液。缓冲层包括记忆金属与含有锑，锡，铋，铝，锗，硅或砷的合金元素的合金。顶部电极设置在缓冲层上方并提供存储金属的源。

2. 发明授权

US6017816A Method of fabricating A1N anti-reflection coating on metal layer 失效
标题翻译：在金属层上制造AlN防反射涂层的方法
公开(公告)号：US6017816A
公开(公告)日：2000-01-25
申请号：US805295
申请日：1997-02-25
申请人： Chyi-Tsong Ni , Kuei-Chang Tsai
发明人： Chyi-Tsong Ni , Kuei-Chang Tsai
IPC分类号： H01L21/027 , H01L21/285 , H01L21/318 , H01L21/3213 , H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0276 , H01L21/28568 , H01L21/318 , H01L21/32137 , Y10S438/907 , Y10S438/913 , Y10S438/952
摘要： A method of fabricating notching free metal interconnection lines by utilizing aluminum nitride (AlN) as an anti-reflection coating. First, field oxide regions are formed on a semiconductor silicon wafer. Then, electrical element structures such as transistor, capacitor and resistor are formed on the predetermined area. Next, a barrier layer, a metal layer and an anti-reflection layer are successively deposited overlaying the entire silicon wafer surface. Next, the photoresist pattern is formed by the conventional lithography technique. By using photoresist pattern as an etching protection mask, the barrier layer, metal layer and anti-reflection layer are also patterned to form metal interconnection lines. Thereafter, the photoresist is stripped by oxygen plasma and sulfuric acid.
摘要翻译：一种通过利用氮化铝（AlN）作为抗反射涂层来制造无缝金属互连线的方法。首先，在半导体硅晶片上形成场氧化物区域。然后，在预定区域上形成诸如晶体管，电容器和电阻器的电气元件结构。接下来，在整个硅晶片表面上依次沉积阻挡层，金属层和抗反射层。接下来，通过常规的光刻技术形成光致抗蚀剂图案。通过使用光致抗蚀剂图案作为蚀刻保护掩模，阻挡层，金属层和抗反射层也被图案化以形成金属互连线。此后，通过氧等离子体和硫酸剥离光致抗蚀剂。

3. 发明授权

US07300745B2 Use of pedestals to fabricate contact openings 失效
标题翻译：使用基座制作接触孔
公开(公告)号：US07300745B2
公开(公告)日：2007-11-27
申请号：US10772520
申请日：2004-02-04
申请人： Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel C. Wang
发明人： Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel C. Wang
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L27/11539 , H01L27/115 , H01L27/11526
摘要： Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.
摘要翻译：非易失性存储器字线（160）形成为控制栅极结构（280）的侧壁上的侧壁间隔物。每个控制栅极结构可以包含浮动和控制栅极（120,140）或一些其它元件。在用于字线的导电层（160）被沉积之前，基座（340）形成为与控制栅极结构相邻。基座将有助于形成将在上覆电介质（310）中蚀刻的接触开口（330.1），以形成与字线的接触。基座可以是虚拟结构。基座可以物理接触两个字线。

4. 发明申请

US20060211255A1 Use of multiple etching steps to reduce lateral etch undercut 审中-公开
标题翻译：使用多个蚀刻步骤来减少横向蚀刻底切
公开(公告)号：US20060211255A1
公开(公告)日：2006-09-21
申请号：US11432222
申请日：2006-05-10
申请人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
发明人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
IPC分类号： H01L21/302
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11539
摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.
摘要翻译：在集成电路制造中，使用具有侧向分量的蚀刻。例如，蚀刻可以是各向同性的。在层（160）的各向同性蚀刻之前，执行相同层的另一蚀刻。这种其他蚀刻可以是各向异性的。该蚀刻攻击通过各向同性蚀刻形成的与特征相邻的层的部分（160×2）。该部分被各向异性蚀刻完全或部分地去除。然后，各向同性蚀刻掩模（420）被形成为延伸超过经过各向异性蚀刻的部分的位置的特征。如果完全去除该部分，则各向同性蚀刻掩模可以完全密封要在该部分侧面上形成的特征，因此不会发生横向蚀刻。如果该部分仅部分被去除，则横向底切将被阻碍，因为在各向同性蚀刻掩模下的特征的通过将变窄。

5. 发明授权

US07375027B2 Method of providing contact via to a surface 有权
标题翻译：将接触通孔提供到表面的方法
公开(公告)号：US07375027B2
公开(公告)日：2008-05-20
申请号：US10964317
申请日：2004-10-12
申请人： Kuei-Chang Tsai , Chunyuan Chao , Chia-Shun Hsiao
发明人： Kuei-Chang Tsai , Chunyuan Chao , Chia-Shun Hsiao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76805 , H01L21/76802 , H01L21/76831
摘要： A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an initial etch through an interlayer dielectric is performed to create an initial via which extends toward, but not into the substrate. At least a portion of the protective layer is retained on the substrate. In another step, the final contact via is created. During this step the protective layer is penetrated to open a via to the surface of the semiconductor material.
摘要翻译：提供了通过半导体材料的表面的接触通孔，该接触通孔具有通过各向异性蚀刻放置在通孔上的电介质层产生的侧壁。在半导体材料的表面上设置有保护层。为了保护衬底，进行通过层间电介质的初始蚀刻，以产生向衬底延伸但不延伸到衬底中的初始通孔。保护层的至少一部分保留在基板上。在另一步中，创建最终的联系人通道。在该步骤期间，保护层被穿透以将通孔打开到半导体材料的表面。

6. 发明申请

US20060079080A1 Method of providing contact via to a surface 有权
标题翻译：将接触通孔提供到表面的方法
公开(公告)号：US20060079080A1
公开(公告)日：2006-04-13
申请号：US10964317
申请日：2004-10-12
申请人： Kuei-Chang Tsai , Chunyuan Chao , Chia-Shun Hsiao
发明人： Kuei-Chang Tsai , Chunyuan Chao , Chia-Shun Hsiao
IPC分类号： H01L21/4763
CPC分类号： H01L21/76805 , H01L21/76802 , H01L21/76831
摘要： A contact via to a surface of a semiconductor material is provided, the contact via having a sidewall which is produced by anisotropically etching a dielectric layer which is placed on via openings. A protective layer is provided on the surface of the semiconductor material. To protect the substrate, an initial etch through an interlayer dielectric is performed to create an initial via which extends toward, but not into the substrate. At least a portion of the protective layer is retained on the substrate. In another step, the final contact via is created. During this step the protective layer is penetrated to open a via to the surface of the semiconductor material.
摘要翻译：提供了通过半导体材料的表面的接触通孔，该接触通孔具有通过各向异性蚀刻放置在通孔上的电介质层产生的侧壁。在半导体材料的表面上设置保护层。为了保护衬底，进行通过层间电介质的初始蚀刻，以产生向衬底延伸但不延伸到衬底中的初始通孔。保护层的至少一部分保留在基板上。在另一步中，创建最终的联系人通道。在该步骤期间，保护层被穿透以将通孔打开到半导体材料的表面。

7. 发明授权

US07297628B2 Dynamically controllable reduction of vertical contact diameter through adjustment of etch mask stack for dielectric etch 有权
标题翻译：通过调整用于电介质蚀刻的蚀刻掩模叠层来动态控制垂直接触直径的减小
公开(公告)号：US07297628B2
公开(公告)日：2007-11-20
申请号：US10718320
申请日：2003-11-19
申请人： Chunyuan Chao , Kuei-Chang Tsai , George A. Kovall
发明人： Chunyuan Chao , Kuei-Chang Tsai , George A. Kovall
IPC分类号： H01L21/4763
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/76816
摘要： Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielectric region (ILD) provided beneath the ARC layer. In one embodiment, the ILD separates an active layers set of an integrated circuit from its first major interconnect layer. Further in one embodiment, a taper-inducing etch recipe is used to create the inwardly-tapered ARC openings, where the etch recipe uses a mixture of CF4 and CHF3 and where the CF4/CHF3 volumetric inflow ratio is substantially less than 5 to 1, and more preferably closer to 1 to 1.
摘要翻译：在设置在图案化光致抗蚀剂层下方的防反射涂层（ARC层）中产生向内锥形的开口。向内锥形开口的较小的底部宽度尺寸用于限定在ARC层下方设置的层间介质区域（ILD）中的另外的开口。在一个实施例中，ILD将集成电路的有源层集合与其第一主互连层分开。此外，在一个实施例中，锥形诱导蚀刻配方用于产生向内锥形的ARC开口，其中蚀刻配方使用CF4和CHF3的混合物，其中CF4 / CHF3体积流入比基本上小于5:1，更优选更接近1比1。

8. 发明授权

US07071115B2 Use of multiple etching steps to reduce lateral etch undercut 有权
公开(公告)号：US07071115B2
公开(公告)日：2006-07-04
申请号：US10772932
申请日：2004-02-04
申请人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel C. Wang
发明人： Chunchieh Huang , Chia-Shun Hsiao , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel C. Wang
IPC分类号： H01L21/302 , H01L21/461 , H01L21/44 , H01L21/76
CPC分类号： H01L27/105 , H01L27/115 , H01L27/11526 , H01L27/11539
摘要： In integrated circuit fabrication, an etch is used that has a lateral component. For example, the etch may be isotropic. Before the isotropic etch of a layer (160), another etch of the same layer is performed. This other etch can be anisotropic. This etch attacks a portion (160X2) of the layer adjacent to the feature to be formed by the isotropic etch. That portion is entirely or partially removed by the anisotropic etch. Then the isotropic etch mask (420) is formed to extend beyond the feature over the location of the portion subjected to the anisotropic etch. If that portion was removed entirely, then the isotropic etch mask may completely seal off the feature to be formed on the side of that portion, so the lateral etching will not occur. If that portion was removed only partially, then the lateral undercut will be impeded because the passage to the feature under the isotropic etch mask will be narrowed.

9. 发明授权

US06984574B2 Cobalt silicide fabrication using protective titanium 有权
标题翻译：使用保护钛的硅化硅制造
公开(公告)号：US06984574B2
公开(公告)日：2006-01-10
申请号：US10056154
申请日：2002-01-23
申请人： Vincent Fortin , Kuei-Chang Tsai
发明人： Vincent Fortin , Kuei-Chang Tsai
IPC分类号： H01L21/425
CPC分类号： H01L21/28518 , H01L21/2855
摘要： A cobalt silicide fabrication process entails first depositing a cobalt layer (120) on a silicon-containing EPROM region. A titanium layer (130) is formed over the cobalt layer by ionized physical vapor deposition (“IPVD”) to protect the cobalt layer from contaminant gases. Cobalt of the cobalt layer is reacted with silicon of the EPROM region to form a cobalt silicide layer (210) after which the titanium layer and any unreacted cobalt are removed. Use of IPVD to form the titanium layer by improves the step coverage to produce a better cobalt silicide layer.
摘要翻译：钴硅化物制造工艺需要首先在含硅EPROM区域上沉积钴层（120）。通过电离物理气相沉积（“IPVD”）在钴层上形成钛层（130），以保护钴层免受污染气体的影响。钴层的钴与EPROM区的硅反应形成硅化钴层（210），然后除去钛层和任何未反应的钴。通过提高步骤覆盖度以产生更好的硅化钴层，使用IPVD来形成钛层。

10. 发明申请

US20050170578A1 Use of pedestals to fabricate contact openings 失效
标题翻译：使用基座制作接触孔
公开(公告)号：US20050170578A1
公开(公告)日：2005-08-04
申请号：US10772520
申请日：2004-02-04
申请人： Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
发明人： Chia-Shun Hsiao , Chunchieh Huang , Jin-Ho Kim , Kuei-Chang Tsai , Barbara Haselden , Daniel Wang
IPC分类号： H01L21/76 , H01L21/8238 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/11539 , H01L27/115 , H01L27/11526
摘要： Nonvolatile memory wordlines (160) are formed as sidewall spacers on sidewalls of control gate structures (280). Each control gate structure may contain floating and control gates (120, 140), or some other elements. Pedestals (340) are formed adjacent to the control gate structures before the conductive layer (160) for the wordlines is deposited. The pedestals will facilitate formation of the contact openings (330.1) that will be etched in an overlying dielectric (310) to form contacts to the wordlines. The pedestals can be dummy structures. A pedestal can physically contact two wordlines.
摘要翻译：非易失性存储器字线（160）形成为控制栅极结构（280）的侧壁上的侧壁间隔物。每个控制栅极结构可以包含浮动和控制栅极（120,140）或一些其它元件。在用于字线的导电层（160）被沉积之前，基座（340）形成为与控制栅极结构相邻。基座将有助于形成将在上覆电介质（310）中蚀刻的接触开口（330.1），以形成与字线的接触。基座可以是虚拟结构。基座可以物理接触两个字线。

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