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1. 发明申请

US20080246639A1 Decoding Apparatus and Communications Apparatus 有权
标题翻译：解码装置和通信装置
公开(公告)号：US20080246639A1
公开(公告)日：2008-10-09
申请号：US11791996
申请日：2005-12-01
申请人： Rui Sakai , Wataru Matsumoto , Yoshikuni Miyata , Hideo Yoshida , Takahiko Nakamura
发明人： Rui Sakai , Wataru Matsumoto , Yoshikuni Miyata , Hideo Yoshida , Takahiko Nakamura
IPC分类号： H03M7/00
CPC分类号： H03M13/1188 , H03M13/1117 , H03M13/112 , H03M13/1137 , H03M13/114 , H03M13/118 , H03M13/1185 , H03M13/3911 , H03M13/6583 , H04L1/005 , H04L1/0057
摘要： A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.
摘要翻译：解码装置包括：行处理单元5和列处理单元6，用于对接收到的信号进行低密度奇偶校验，根据最小和算法对行处理和列处理进行概率信息的计算和更新以1比特或预定比特数的批次编码的解码结果判断单元8，用于从后验值的硬判定中确定解码结果，用于对解码结果进行奇偶校验，并判断是否解码结果是正确的，以及控制单元，用于根据解码结果判断单元8的判断结果控制行处理单元5和列处理单元6的解码处理的迭代。

2. 发明授权

US08201047B2 Decoding apparatus and communications apparatus 有权
标题翻译：解码装置和通信装置
公开(公告)号：US08201047B2
公开(公告)日：2012-06-12
申请号：US11791996
申请日：2005-12-01
申请人： Rui Sakai , Wataru Matsumoto , Yoshikuni Miyata , Hideo Yoshida , Takahiko Nakamura
发明人： Rui Sakai , Wataru Matsumoto , Yoshikuni Miyata , Hideo Yoshida , Takahiko Nakamura
IPC分类号： H03M13/00
CPC分类号： H03M13/1188 , H03M13/1117 , H03M13/112 , H03M13/1137 , H03M13/114 , H03M13/118 , H03M13/1185 , H03M13/3911 , H03M13/6583 , H04L1/005 , H04L1/0057
摘要： A decoding apparatus includes a row processing unit 5 and a column processing unit 6 for performing a calculation and an update of probability information with row processing and column processing according to a Min-Sum algorithm on a received signal which is low-density parity-check coded in batches of 1 bit or a predetermined number of bits, a decoded result judgment unit 8 for determining a decoded result from a hard decision of a posterior value, for performing a parity check on the decoded result, and for judging whether or not the decoded result is correct, and a control unit for controlling iteration of decoding processing by the row processing unit 5 and column processing unit 6 on the basis of the judgment result of the decoded result judgment unit 8.
摘要翻译：解码装置包括：行处理单元5和列处理单元6，用于对接收到的信号进行低密度奇偶校验，根据最小和算法对行处理和列处理进行概率信息的计算和更新以1比特或预定比特数的批次编码的解码结果判断单元8，用于从后验值的硬判定中确定解码结果，用于对解码结果进行奇偶校验，并判断是否解码结果是正确的，以及控制单元，用于根据解码结果判断单元8的判断结果控制行处理单元5和列处理单元6的解码处理的迭代。

3. 发明授权

US08103935B2 Test matrix generating method, encoding method, decoding method, communication apparatus, communication system, encoder and decoder 有权
标题翻译：测试矩阵生成方法，编码方法，解码方法，通信装置，通信系统，编码器和解码器
公开(公告)号：US08103935B2
公开(公告)日：2012-01-24
申请号：US12063507
申请日：2006-07-31
申请人： Wataru Matsumoto , Rui Sakai , Hideo Yoshida , Takahiko Nakamura , Yoshikuni Miyata
发明人： Wataru Matsumoto , Rui Sakai , Hideo Yoshida , Takahiko Nakamura , Yoshikuni Miyata
IPC分类号： G06F11/00
CPC分类号： H03M13/116 , H03M13/1117 , H03M13/1122 , H03M13/1137 , H03M13/6362 , H04L1/0057
摘要： A regular quasi-cyclic matrix is prepared, a conditional expression for assuring a predetermined minimum loop in a parity check matrix is derived, and a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expression and a predetermined weight distribution is generated. The specific cyclic permutation matrix is converted into the zero-matrix to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.
摘要翻译：准备规则准循环矩阵，导出用于确定奇偶校验矩阵中的预定最小循环的条件表达式，以及用于将特定循环置换矩阵转换成基于条件表达式的零矩阵的掩码矩阵，产生重量分布。特定的循环置换矩阵被转换为零矩阵以产生不规则的掩蔽准循环矩阵。其中掩蔽准循环矩阵和其中循环置换矩阵以阶梯排列的矩阵布置在预定位置的不规则奇偶校验矩阵。

4. 发明申请

US20090265600A1 TEST MATRIX GENERATING METHOD, ENCODING METHOD, DECODING METHOD, COMMUNICATION APPARATUS, COMMUNICATION SYSTEM, ENCODER AND DECODER 有权
标题翻译：测试矩阵生成方法，编码方法，解码方法，通信设备，通信系统，编码器和解码器
公开(公告)号：US20090265600A1
公开(公告)日：2009-10-22
申请号：US12063507
申请日：2006-07-31
申请人： Wataru Matsumoto , Rui Sakai , Hideo Yoshida , Takahiko Nakamura , Yoshikuni Miyata
发明人： Wataru Matsumoto , Rui Sakai , Hideo Yoshida , Takahiko Nakamura , Yoshikuni Miyata
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： H03M13/116 , H03M13/1117 , H03M13/1122 , H03M13/1137 , H03M13/6362 , H04L1/0057
摘要： A regular quasi-cyclic matrix is prepared, a conditional expression for assuring a predetermined minimum loop in a parity check matrix is derived, and a mask matrix for converting a specific cyclic permutation matrix into a zero-matrix based on the conditional expression and a predetermined weight distribution is generated. The specific cyclic permutation matrix is converted into the zero-matrix to generate an irregular masking quasi-cyclic matrix. An irregular parity check matrix in which the masking quasi-cyclic matrix and a matrix in which the cyclic permutation matrices are arranged in a staircase manner are arranged in a predetermined location.
摘要翻译：准备规则准循环矩阵，导出用于确定奇偶校验矩阵中的预定最小循环的条件表达式，以及用于将特定循环置换矩阵转换成基于条件表达式的零矩阵的掩码矩阵，产生重量分布。特定的循环置换矩阵被转换为零矩阵以产生不规则的掩蔽准循环矩阵。其中掩蔽准循环矩阵和其中循环置换矩阵以阶梯排列的矩阵布置在预定位置的不规则奇偶校验矩阵。

5. 发明授权

US08132080B2 Communication apparatus and decoding method 有权
标题翻译：通信设备和解码方法
公开(公告)号：US08132080B2
公开(公告)日：2012-03-06
申请号：US11988565
申请日：2006-07-12
申请人： Wataru Matsumoto , Rui Sakai , Hideo Yoshida , Yoshikuni Miyata
发明人： Wataru Matsumoto , Rui Sakai , Hideo Yoshida , Yoshikuni Miyata
IPC分类号： H03M13/45
CPC分类号： H03M13/1122 , H03M13/1117 , H03M13/112 , H03M13/6561 , H03M13/658 , H03M13/6583
摘要： A communication apparatus includes a storage unit, a row processing unit, and a column processing unit. The row processing unit repeatedly performs row processing to calculate a column-processing LLR for each column and each row in a check matrix. The column processing unit calculates a row-processing LLR for each column and each row of the check matrix, and repeatedly performs column processing to store in the storage unit the minimum value k of absolute values of the row-processing LLR. The row processing unit and the column processing unit alternately performs their processing. The row processing unit performs calculation using an approximate minimum value while the column processing unit cyclically updates the minimum k value of each row.
摘要翻译：通信装置包括存储单元，行处理单元和列处理单元。行处理单元重复执行行处理，以计算校验矩阵中的每列和每行的列处理LLR。列处理单元针对每个列和校验矩阵的每一行计算行处理LLR，并且重复执行列处理，以在存储单元中存储行处理LLR的绝对值的最小值k。行处理单元和列处理单元交替执行其处理。行处理单元使用近似最小值执行计算，而列处理单元循环地更新每行的最小k值。

6. 发明申请

US20090132887A1 Communication Apparatus and Decoding Method 有权
标题翻译：通信设备和解码方法
公开(公告)号：US20090132887A1
公开(公告)日：2009-05-21
申请号：US11988565
申请日：2006-07-12
申请人： Wataru Matsumoto , Rui Sakai , Hideo Yoshida , Yoshikuni Miyata
发明人： Wataru Matsumoto , Rui Sakai , Hideo Yoshida , Yoshikuni Miyata
IPC分类号： H03M13/05 , G06F11/07
CPC分类号： H03M13/1122 , H03M13/1117 , H03M13/112 , H03M13/6561 , H03M13/658 , H03M13/6583
摘要： A communication apparatus includes a storage unit, a row processing unit, and a column processing unit. The row processing unit repeatedly performs row processing to calculate a column-processing LLR for each column and each row in a check matrix. The column processing unit calculates a row-processing LLR for each column and each row of the check matrix, and repeatedly performs column processing to store in the storage unit the minimum value k of absolute values of the row-processing LLR. The row processing unit and the column processing unit alternately performs their processing. The row processing unit performs calculation using an approximate minimum value while the column processing unit cyclically updates the minimum k value of each row.
摘要翻译：通信装置包括存储单元，行处理单元和列处理单元。行处理单元重复执行行处理，以计算校验矩阵中的每列和每行的列处理LLR。列处理单元针对每个列和校验矩阵的每一行计算行处理LLR，并且重复执行列处理，以在存储单元中存储行处理LLR的绝对值的最小值k。行处理单元和列处理单元交替执行其处理。行处理单元使用近似最小值执行计算，而列处理单元循环地更新每行的最小k值。

7. 发明授权

US07069496B2 Decoding method, decoding apparatus and digital transmission system of product code 失效
公开(公告)号：US07069496B2
公开(公告)日：2006-06-27
申请号：US10284391
申请日：2002-10-31
申请人： Hachiro Fujita , Yoshikuni Miyata , Takahiko Nakamura , Hideo Yoshida
发明人： Hachiro Fujita , Yoshikuni Miyata , Takahiko Nakamura , Hideo Yoshida
IPC分类号： H03M13/00
CPC分类号： H04L1/0066 , H03M13/136 , H03M13/151 , H03M13/152 , H03M13/19 , H03M13/2909 , H03M13/2927 , H03M13/2948 , H03M13/3738 , H03M13/45 , H03M13/451 , H03M13/6306 , H03M13/6561 , H04L1/005 , H04L1/1835 , H04L1/1874
摘要： A decoding apparatus generates error position sets of data sequence by generating a codeword from positions of soft input values output from a low reliability position detecting circuit and from syndromes computed by a syndrome calculation circuit. The recording apparatus further includes a codeword candidate generating circuit that computes correlation mismatch amounts by adding soft input values at the error positions contained in the error position sets, and updates the correction information according to the error position sets and correlation mismatch amounts. The decoding apparatus can calculate the soft output values accurately by utilizing the generated codeword candidates efficiently, and reduce the circuit scale by decreasing the amount of computation.

8. 发明授权

US06912684B2 Error correction encoding method and apparatus, and error correction decoding method and apparatus 失效
标题翻译：纠错编码方法和装置，以及纠错解码方法和装置
公开(公告)号：US06912684B2
公开(公告)日：2005-06-28
申请号：US10097347
申请日：2002-03-15
申请人： Yoshikuni Miyata , Hachiro Fujita , Takahiko Nakamura , Hideo Yoshida
发明人： Yoshikuni Miyata , Hachiro Fujita , Takahiko Nakamura , Hideo Yoshida
IPC分类号： G06F11/10 , H03M13/23 , H03M13/29 , H03M13/00
CPC分类号： H03M13/2987 , H03M13/2957 , H03M13/2963 , H03M13/2972 , H03M13/2981 , H03M13/3776
摘要： An error correction encoding method and apparatus, and an error correction decoding method and apparatus are provided without requiring transmission of tail bits. A turbo encoding step (ST41-ST45) and a transmission termination processing step (ST46→ST44-ST47) are included. In the turbo encoding step, a transmission information bit sequence is divided into a plurality of frames. Registers in each recursive systematic convolutional encoder are initialized before turbo encoding of a first frame. After turbo encoding of the first frame is carried out, a second frame and following frames are continuously subjected to turbo encoding without initializing the registers in each recursive systematic convolutional encoder before the turbo encoding of the second frame and following frames. In a transmission termination processing step, tail bits for initializing the registers in each recursive systematic convolutional encoder are calculated only after a final frame has been subjected to turbo encoding.
摘要翻译：提供纠错编码方法和装置以及纠错解码方法和装置，而不需要传输尾比特。包括turbo编码步骤（ST 41 -ST 45）和发送终止处理步骤（ST 46-> ST 44 -ST 47）。在turbo编码步骤中，发送信息比特序列被分成多个帧。每个递归系统卷积编码器中的寄存器在第一帧的turbo编码之前被初始化。在执行第一帧的turbo编码之后，在第二帧和后续帧的turbo编码之前，第二帧和后续帧被连续地进行turbo编码，而不在每个递归系统卷积编码器中初始化寄存器。在传输终止处理步骤中，仅在最后一帧已进行turbo编码之后才计算用于初始化每个递归系统卷积编码器中的寄存器的尾比特。

9. 发明授权

US06658605B1 Multiple coding method and apparatus, multiple decoding method and apparatus, and information transmission system 有权
标题翻译：多重编码方法和装置，多重解码方法和装置以及信息传输系统
公开(公告)号：US06658605B1
公开(公告)日：2003-12-02
申请号：US09703638
申请日：2000-11-02
申请人： Hideo Yoshida , Takahiko Nakamura , Hachiro Fujita , Yoshikuni Miyata , Kazuo Kubo
发明人： Hideo Yoshida , Takahiko Nakamura , Hachiro Fujita , Yoshikuni Miyata , Kazuo Kubo
IPC分类号： G11C2900
CPC分类号： H03M7/30 , H03M13/15 , H03M13/1515 , H03M13/2707 , H03M13/2721 , H03M13/29 , H03M13/6561
摘要： A multiple coding apparatus comprises a first encoder for encoding a plurality of input sequences in parallel so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of input sequences. An interleaving circuit interleaves the plurality of output coded sequences applied thereto in parallel from the first encoder without having to use any memory. The interleaving circuit permutes the plurality of input sequences on a bit-by-bit or symbol-by-symbol basis so as to generate a plurality of interleaved coded sequences in parallel. A second encoder then encodes the plurality of interleaved coded sequences applied thereto in parallel from the interleaving circuit so as to generate a plurality of output coded sequences in parallel while adding an error-correcting bit sequence to each of the plurality of interleaved coded sequences.
摘要翻译：多重编码装置包括：并行地编码多个输入序列的第一编码器，以便并行地产生多个输出编码序列，同时向多个输入序列中的每个输入序列添加纠错位序列。交织电路将从第一编码器并行地施加到其上的多个输出编码序列进行交织，而不必使用任何存储器。交织电路逐位或逐符号地排列多个输入序列，以便并行地生成多个交错编码序列。然后，第二编码器对从交织电路并行施加到其上的多个交错编码序列进行编码，以便并行地产生多个输出编码序列，同时向多个交错编码序列中的每一个添加纠错位序列。

10. 发明申请

US20130311847A1 ERROR CORRECTION CODING DEVICE, ERROR CORRECTION DECODING DEVICE AND METHOD THEREFOR 有权
标题翻译：错误校正编码装置，错误校正解码装置及其方法
公开(公告)号：US20130311847A1
公开(公告)日：2013-11-21
申请号：US13982919
申请日：2012-05-30
申请人： Yoshikuni Miyata , Wataru Matsumoto , Hideo Yoshida , Kazuo Kubo
发明人： Yoshikuni Miyata , Wataru Matsumoto , Hideo Yoshida , Kazuo Kubo
IPC分类号： H03M13/29
CPC分类号： H03M13/29 , H03M13/1102 , H03M13/1145 , H03M13/152 , H03M13/2909 , H03M13/356
摘要： Provided is an error correction encoder that performs coding on both a transmission area and a redundancy area of the transmission frame by using a product code, and when excess or deficiency is arisen with respect to allocation of an information sequence area and/or a parity sequence area in a product code frame generated by the coding using the product code, non-uniformly allocate the information sequence area to the parity sequence area, and/or non-uniformly allocate the parity sequence area to the information sequence area, where each of the non-uniform allocations is performed in accordance with the arisen excess or deficiency.
摘要翻译：提供了一种纠错编码器，其通过使用产品代码对发送帧的发送区域和冗余区域两者进行编码，并且当相对于信息序列区域和/或奇偶校验序列的分配产生过多或不足时通过使用产品代码的编码生成的商品代码帧中的区域，将信息序列区域均匀地分配给奇偶校验序列区域，和/或非均匀地将奇偶校验序列区域分配给信息序列区域，其中，根据发生的过量或不足，进行非均匀分配。

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