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1. 发明授权

US09570467B2 High voltage three-dimensional devices having dielectric liners 有权
标题翻译：具有电介质衬垫的高压三维器件
公开(公告)号：US09570467B2
公开(公告)日：2017-02-14
申请号：US14641117
申请日：2015-03-06
申请人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
发明人： Walid M. Hafez , Jeng-Ya D. Yeh , Curtis Tsai , Joodong Park , Chia-Hong Jan , Gopinath Bhimarasetti
IPC分类号： H01L21/84 , H01L27/12 , H01L29/66 , H01L21/8234 , H01L21/02 , H01L21/28 , H01L29/423 , H01L29/51
CPC分类号： H01L27/1211 , H01L21/02164 , H01L21/0228 , H01L21/02532 , H01L21/02598 , H01L21/28158 , H01L21/823412 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823462 , H01L21/823468 , H01L21/845 , H01L29/42356 , H01L29/51 , H01L29/513 , H01L29/66545 , H01L29/6656 , H01L29/6681
摘要： High voltage three-dimensional devices having dielectric liners and methods of forming high voltage three-dimensional devices having dielectric liners are described. For example, a semiconductor structure includes a first fin active region and a second fin active region disposed above a substrate. A first gate structure is disposed above a top surface of, and along sidewalls of, the first fin active region. The first gate structure includes a first gate dielectric, a first gate electrode, and first spacers. The first gate dielectric is composed of a first dielectric layer disposed on the first fin active region and along sidewalls of the first spacers, and a second, different, dielectric layer disposed on the first dielectric layer and along sidewalls of the first spacers. The semiconductor structure also includes a second gate structure disposed above a top surface of, and along sidewalls of, the second fin active region. The second gate structure includes a second gate dielectric, a second gate electrode, and second spacers. The second gate dielectric is composed of the second dielectric layer disposed on the second fin active region and along sidewalls of the second spacers.
摘要翻译：描述了具有电介质衬垫的高压三维器件和形成具有电介质衬垫的高电压三维器件的方法。例如，半导体结构包括设置在基板上方的第一鳍状物活性区域和第二鳍状物活性区域。第一栅极结构设置在第一鳍片活动区域的顶表面之上并且沿着第一鳍片活动区域的侧壁的上方。第一栅极结构包括第一栅极电介质，第一栅极电极和第一间隔物。第一栅极电介质由设置在第一鳍状物活性区域上并沿着第一间隔物的侧壁的第一介电层和设置在第一介电层上并沿着第一间隔物的侧壁的第二不同介电层组成。半导体结构还包括第二栅极结构，其设置在第二鳍片活动区域的顶表面之上并且沿着第二鳍片活动区域的侧壁的上方。第二栅极结构包括第二栅极电介质，第二栅电极和第二间隔物。第二栅极电介质由设置在第二鳍状物活性区域和第二间隔物的侧壁上的第二介电层构成。

2. 发明申请

US20170005187A1 FIN-BASED SEMICONDUCTOR DEVICES AND METHODS 审中-公开
标题翻译：基于FIN的半导体器件和方法
公开(公告)号：US20170005187A1
公开(公告)日：2017-01-05
申请号：US15100286
申请日：2014-01-24
申请人： Walid M. Hafez , Chia-Hong Jan
发明人： Walid M. Hafez , Chia-Hong Jan
IPC分类号： H01L29/74 , H01L29/66 , H01L29/417 , H01L27/02 , H01L29/06
CPC分类号： H01L29/74 , H01L21/2255 , H01L27/0262 , H01L29/0649 , H01L29/41716 , H01L29/66363 , H01L29/785
摘要： Embodiments of semiconductor devices, integrated circuit devices and methods are disclosed. In some embodiments, a semiconductor device may include a first fin and a second fin disposed on a substrate. The first fin may have a portion including a first material disposed between a second material and the substrate, the second material disposed between a third material and the first material, and the third material disposed between a fourth material and the second material. The first and third materials may be formed from a first type of extrinsic semiconductor, and the second and fourth materials may be formed from a second, different type of extrinsic semiconductor. The second fin may be laterally separated from the first fin and materially contiguous with at least one of the first, second, third or fourth materials. Other embodiments may be disclosed and/or claimed.
摘要翻译：公开了半导体器件，集成电路器件和方法的实施例。在一些实施例中，半导体器件可以包括设置在衬底上的第一鳍和第二鳍。第一翅片可以具有包括设置在第二材料和基底之间的第一材料的部分，第二材料设置在第三材料和第一材料之间，第三材料设置在第四材料和第二材料之间。第一和第三材料可以由第一类型的非本征半导体形成，并且第二和第四材料可以由第二种不同类型的外在半导体形成。第二翅片可以与第一翅片横向分离并且与第一，第二，第三或第四材料中的至少一个物质连接。可以公开和/或要求保护其他实施例。

3. 发明申请

US20150187709A1 METAL FUSE BY TOPOLOGY 有权
标题翻译：金属保险丝通过拓扑学
公开(公告)号：US20150187709A1
公开(公告)日：2015-07-02
申请号：US14142629
申请日：2013-12-27
申请人： Chen-Guan Lee , Walid M. Hafez , Chia-Hong Jan
发明人： Chen-Guan Lee , Walid M. Hafez , Chia-Hong Jan
IPC分类号： H01L23/62 , H01L21/3205 , H01L21/02
CPC分类号： H01L23/62 , H01L21/0217 , H01L21/32055 , H01L23/5256 , H01L2224/16225 , H01L2924/0002 , H01L2924/15311 , H01L2924/00
摘要： Embodiments of the present disclosure describe techniques and configurations for overcurrent fuses in integrated circuit (IC) devices. In one embodiment, a device layer of a die may include a first line structure with a recessed portion between opposite end portions and two second line structures positioned on opposite sides of the first line structure. An isolation material may be disposed in the gaps between the line structures and in a first recess defined by the recessed portion. The isolation material may have a recessed portion that defines a second recess in the first recess, and a fuse structure may be disposed in the second recess. Other embodiments may be described and/or claimed.
摘要翻译：本公开的实施例描述了用于集成电路（IC）装置中的过电流保险丝的技术和配置。在一个实施例中，管芯的器件层可以包括在相对端部之间具有凹陷部分的第一线结构和位于第一线结构的相对侧上的两个第二线结构。隔离材料可以设置在线结构之间的间隙中，并且可以设置在由凹部限定的第一凹部中。隔离材料可以具有限定第一凹部中的第二凹部的凹部，并且熔丝结构可以设置在第二凹部中。可以描述和/或要求保护其他实施例。

4. 发明申请

US20140308785A1 PRECISION RESISTOR FOR NON-PLANAR SEMICONDUCTOR DEVICE ARCHITECTURE 有权
公开(公告)号：US20140308785A1
公开(公告)日：2014-10-16
申请号：US14313678
申请日：2014-06-24
申请人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
发明人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
IPC分类号： H01L21/8234 , H01L29/66 , H01L49/02
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0886 , H01L28/20 , H01L29/66545 , H01L29/66795
摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

5. 发明申请

US20110215422A1 PENETRATING IMPLANT FOR FORMING A SEMICONDUCTOR DEVICE 有权
标题翻译：用于形成半导体器件的移植植入物
公开(公告)号：US20110215422A1
公开(公告)日：2011-09-08
申请号：US13107783
申请日：2011-05-13
申请人： Giuseppe Curello , Ian R. Post , Nick Lindert , Walid M. Hafez , Chia-Hong Jan , Mark T. Bohr
发明人： Giuseppe Curello , Ian R. Post , Nick Lindert , Walid M. Hafez , Chia-Hong Jan , Mark T. Bohr
IPC分类号： H01L21/8238 , H01L29/36 , H01L29/78
CPC分类号： H01L29/66477 , H01L21/823412 , H01L21/823425 , H01L21/823456 , H01L21/823493 , H01L29/6659 , H01L29/7833 , Y10S438/918
摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.
摘要翻译：描述了形成半导体器件的半导体器件和方法。半导体包括设置在基板上的栅极堆叠。尖端区域设置在栅极堆叠的任一侧上的衬底中。卤素区域设置在邻近尖端区域的衬底中。阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

6. 发明授权

US10090304B2 Isolation well doping with solid-state diffusion sources for FinFET architectures 有权
公开(公告)号：US10090304B2
公开(公告)日：2018-10-02
申请号：US14914614
申请日：2013-09-25
申请人： Walid M. Hafez , Chia-Hong Jan , Jeng-Ya D. Yeh , Hsu-Yu Chang , Neville Dias , Chanaka Munasinghe
发明人： Chia-Hong Jan , Walid M Hafez , Jeng-Ya David Yeh , Hsu-Yu Chang , Neville L Dias , Chanaka D Munasinghe
IPC分类号： H01L27/088 , H01L27/12 , H01L29/78 , H01L27/092 , H01L21/8238 , H01L29/66 , H01L21/225 , H01L29/06 , H01L29/08 , H01L29/10
摘要： An impurity source film is formed along a portion of a non-planar semiconductor fin structure. The impurity source film may serve as source of an impurity that becomes electrically active subsequent to diffusing from the source film into the semiconductor fin. In one embodiment, an impurity source film is disposed adjacent to a sidewall surface of a portion of a sub-fin region disposed between an active region of the fin and the substrate and is more proximate to the substrate than to the active area. In further embodiments, the impurity source film may provide a source of dopant that renders the sub-fin region complementarily doped relative to a region of the substrate forming a P/N junction that is at least part of an isolation structure electrically isolating the active fin region from a region of the substrate.

7. 发明申请

US20140319623A1 METHODS OF INTEGRATING MULTIPLE GATE DIELECTRIC TRANSISTORS ON A TRI-GATE (FINFET) PROCESS 审中-公开
标题翻译：在三极（FINFET）工艺上集成多个栅极介质晶体管的方法
公开(公告)号：US20140319623A1
公开(公告)日：2014-10-30
申请号：US13997624
申请日：2011-12-28
申请人： Curtis Tsai , Chia-Hong Jan , Jeng-Ya David Yeh , Joodong Park , Walid M. Hafez
发明人： Curtis Tsai , Chia-Hong Jan , Jeng-Ya David Yeh , Joodong Park , Walid M. Hafez
IPC分类号： H01L21/8234 , H01L29/423 , H01L27/088
摘要： Two or more types of fin-based transistors having different gate structures and formed on a single integrated circuit are described. The gate structures for each type of transistor are distinguished at least by the thickness or composition of the gate dielectric layer(s) or the composition of the work function metal layer(s) in the gate electrode. Methods are also provided for fabricating an integrated circuit having at least two different types of fin-based transistors, where the transistor types are distinguished by the thickness and composition of the gate dielectric layer(s) and/or the thickness and composition of the work function metal in the gate electrode.
摘要翻译：描述了具有不同栅极结构并形成在单个集成电路上的两种或多种类型的鳍式晶体管。每种类型的晶体管的栅极结构至少区别于栅极电介质层的厚度或组成或栅电极中功函数金属层的组成。还提供了用于制造具有至少两种不同类型的基于鳍的晶体管的集成电路的方法，其中晶体管类型通过栅极电介质层的厚度和组成和/或工件的厚度和组成来区分功能金属在栅电极。

8. 发明授权

US08796772B2 Precision resistor for non-planar semiconductor device architecture 有权
公开(公告)号：US08796772B2
公开(公告)日：2014-08-05
申请号：US13625698
申请日：2012-09-24
申请人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
发明人： Jeng-Ya D. Yeh , Peter J. Vandervoorn , Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park
IPC分类号： H01L21/70
CPC分类号： H01L21/823431 , H01L27/0629 , H01L27/0886 , H01L28/20 , H01L29/66545 , H01L29/66795
摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

9. 发明申请

US20130270559A1 ANTIFUSE ELEMENT UTILIZING NON-PLANAR TOPOLOGY 有权
标题翻译：使用非平面拓扑学的抗体元件
公开(公告)号：US20130270559A1
公开(公告)日：2013-10-17
申请号：US13976087
申请日：2011-10-18
申请人： Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park , Jeng-Ya D. Yeh
发明人： Walid M. Hafez , Chia-Hong Jan , Curtis Tsai , Joodong Park , Jeng-Ya D. Yeh
IPC分类号： H01L27/112
CPC分类号： H01L27/11206 , H01L21/823821 , H01L23/5252 , H01L27/0924 , H01L29/7853 , H01L2924/0002 , H01L2924/00
摘要： Techniques for providing non-volatile antifuse memory elements and other antifuse links are disclosed herein. In sonic embodiments, the antifuse memory elements are configured with non-planar topology such as FinFET topology. In some such embodiments, the fin topology can be manipulated and used to effectively promote lower breakdown voltage transistors, by creating enhanced-emission sites which are suitable for use in lower voltage non-volatile antifuse memory elements. In one example embodiment, a semiconductor antifuse device is provided that includes a non-planar diffusion area having a fin configured with a tapered portion, a dielectric isolation layer on the fin including the tapered portion, and a gate material on the dielectric isolation layer. The tapered portion of the fin may be formed, for instance, by oxidation, etching, and/or ablation, and in some cases includes a base region and a thinned region, and the thinned region is at least 50% thinner than the base region.
摘要翻译：本文公开了用于提供非易失性反熔丝存储元件和其它反熔丝链路的技术。在声音实施例中，反熔丝存储器元件被配置为具有诸如FinFET拓扑的非平面拓扑。在一些这样的实施例中，可以通过产生适合用于较低电压非易失性反熔丝存储器元件的增强发射位点来操纵翅片拓扑并用于有效地促进较低击穿电压晶体管。在一个示例实施例中，提供了一种半导体反熔丝装置，其包括具有锥形部分的翅片的非平面扩散区域，在包括锥形部分的鳍片上的介电隔离层和介电隔离层上的栅极材料。翅片的锥形部分可以例如通过氧化，蚀刻和/或烧蚀形成，并且在一些情况下包括基底区域和变薄区域，并且变薄区域比基底区域薄至少50％。

10. 发明申请

US20130229882A1 PROGRAMMABLE/RE-PROGRAMMABLE DEVICE IN HIGH-K METAL GATE MOS 有权
标题翻译：可编程/可重新编程的高K金属栅MOS器件
公开(公告)号：US20130229882A1
公开(公告)日：2013-09-05
申请号：US13870598
申请日：2013-04-25
申请人： Walid M. Hafez , Anisur Rahman , Chia-Hong Jan
发明人： Walid M. Hafez , Anisur Rahman , Chia-Hong Jan
IPC分类号： G11C7/00 , H03K19/173
CPC分类号： G11C7/00 , G11C17/16 , G11C17/18 , H03K19/173
摘要： Techniques and circuitry are disclosed for implementing non-volatile storage that exploit bias temperature instability (BTI) effects of high-k/metal-gate n-type or p-type metal oxide semiconductor (NMOS or PMOS) transistors. A programmed bitcell of, for example, a memory or programmable logic circuit exhibits a threshold voltage shift resulting from an applied programming bias used to program bitcells. In some cases, applying a first programming bias causes the device to have a first state, and applying a second programming bias causes the device to have a second state that is different than the first state. Programmed bitcells can be erased by applying an opposite polarity stress, and re-programmed through multiple cycles. The bitcell configuration can be used in conjunction with column/row select circuitry and/or readout circuitry, in accordance with some embodiments.
摘要翻译：公开了用于实现利用高k /金属栅极n型或p型金属氧化物半导体（NMOS或PMOS）晶体管的偏置温度不稳定性（BTI）效应的非易失性存储器的技术和电路。例如，存储器或可编程逻辑电路的编程位单元表现出由用于编程位单元的应用编程偏置产生的阈值电压偏移。在一些情况下，施加第一编程偏置使得器件具有第一状态，并且施加第二编程偏置使得器件具有与第一状态不同的第二状态。可以通过施加相反的极性应力来擦除编程的位单元，并通过多个周期重新编程。根据一些实施例，位单元配置可以与列/行选择电路和/或读出电路结合使用。

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