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1. 发明申请

US20080013715A1 Cryptography processing units and multiplier 有权
标题翻译：密码处理单元和乘数
公开(公告)号：US20080013715A1
公开(公告)日：2008-01-17
申请号：US11323993
申请日：2005-12-30
申请人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： H04L9/28
CPC分类号： G06F7/52 , G06F9/3001 , G06F9/3881 , G06F9/3885 , G06F21/72
摘要： In general, in one aspect, the disclosure describes a system including multiple programmable processing units, a dedicated hardware multiplier, and at least one bus connecting the multiple processing units and multiplier.
摘要翻译：通常，在一个方面，本公开描述了包括多个可编程处理单元，专用硬件乘法器和连接多个处理单元和乘法器的至少一个总线的系统。

2. 发明申请

US20070192547A1 Programmable processing unit 有权
标题翻译：可编程处理单元
公开(公告)号：US20070192547A1
公开(公告)日：2007-08-16
申请号：US11354404
申请日：2006-02-14
申请人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal
发明人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F9/30145 , G06F7/5324 , G06F9/3001 , G06F9/30014 , G06F9/30036 , G06F9/3004 , G06F9/383 , G06F21/602 , G06F21/72
摘要： In general, in one aspect, the disclosure describes a processing unit that includes an input buffer to store data received by the processing unit, a memory, an arithmetic logic unit coupled to the input buffer and to the memory, an output buffer; and control logic having access to a control store of program instructions, the control logic to process instructions including an instruction to transfer data from the input buffer to the memory and an instruction to cause the arithmetic logic unit to perform an operation on operands provided by at least one of the memory and the input buffer, the instruction to output results of the operation to at least one of the memory and the output buffer.
摘要翻译：通常，在一个方面，本发明描述了一种处理单元，其包括用于存储由处理单元接收的数据的输入缓冲器，存储器，耦合到输入缓冲器和存储器的算术逻辑单元，输出缓冲器; 以及具有访问程序指令的控制存储的控制逻辑，所述控制逻辑用于处理包括将数据从所述输入缓冲器传送到所述存储器的指令的指令，以及使所述算术逻辑单元对由所述输入缓冲器提供的操作数执行操作的指令至少一个存储器和输入缓冲器，将操作结果输出到至少一个存储器和输出缓冲器的指令。

3. 发明申请

US20070192626A1 Exponent windowing 审中-公开
标题翻译：指数窗口
公开(公告)号：US20070192626A1
公开(公告)日：2007-08-16
申请号：US11647892
申请日：2006-12-28
申请人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F12/14
CPC分类号： G06F21/602
摘要： The disclosure includes description of a processor component that includes a set of register bits to perform a shift register operation. The component window detection logic can detect a window of bits in the set of register bits and, in response to detecting the window, output the window of bits.
摘要翻译：本公开包括描述包括一组寄存器位以执行移位寄存器操作的处理器组件。组件窗口检测逻辑可以检测寄存器位组中的位窗口，并且响应于检测窗口输出位窗口。

4. 发明申请

US20070192571A1 Programmable processing unit providing concurrent datapath operation of multiple instructions 审中-公开
标题翻译：可编程处理单元提供多个指令的并行数据路径操作
公开(公告)号：US20070192571A1
公开(公告)日：2007-08-16
申请号：US11354666
申请日：2006-02-14
申请人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F15/00
CPC分类号： G06F9/30014 , G06F7/5324 , G06F9/30025 , G06F9/30032 , G06F9/3004 , G06F9/30181 , G06F9/3814 , G06F9/383 , G06F9/3836 , G06F9/3851 , G06F9/3857 , G06F9/3885 , G06F9/3897
摘要： In general, in one aspect, the disclosure describes a processing unit that includes a datapath having an input buffer, at least one memory, and an arithmetic logic unit, and control logic having access to a program instruction control store. The control logic controls operation of the datapath and may concurrently cause the datapath to operate in response to different instructions that use different sections of the datapath, wherein the different sections of the datapath comprise a first section transferring data from an input buffer to the memory and a second section transferring data from the memory to the arithmetic logic unit.
摘要翻译：通常，在一个方面，本公开描述了一种处理单元，其包括具有输入缓冲器，至少一个存储器和算术逻辑单元的数据通路，以及具有访问程序指令控制存储器的控制逻辑。控制逻辑控制数据路径的操作并且可以同时使数据路径响应于使用数据路径的不同部分的不同指令来操作，其中数据通路的不同部分包括将数据从输入缓冲器传送到存储器的第一部分，以及第二部分，将数据从存储器传送到算术逻辑单元。

5. 发明申请

US20070174372A1 Programmable processing unit having multiple scopes 失效
标题翻译：具有多个示波器的可编程处理单元
公开(公告)号：US20070174372A1
公开(公告)日：2007-07-26
申请号：US11354670
申请日：2006-02-14
申请人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F15/00
CPC分类号： G06F21/602
摘要： In general, in one aspect, the disclosure describes a processing unit that includes a memory, an arithmetic logic unit, and control logic having access to program instructions of a control store. The control logic includes logic to access multiple sets of variables, variables in the different sets of variables being identically referenced by instructions, associate a one of the sets of variables as the current set of variables to be used in instructions that are executed by the arithmetic logic unit, change the set of variables associated with the current set of variables in response to a procedure call or exit, and alter the value of a variable of a set of the variables other than the set of variables associated with the current set of variables in response to an instruction.
摘要翻译：通常，在一个方面，本公开描述了一种处理单元，其包括存储器，算术逻辑单元和具有访问控制存储器的程序指令的控制逻辑。控制逻辑包括访问多组变量的逻辑，不同变量集合中的变量由指令相同地引用，将变量集合中的一个与当前由算术执行的指令中使用的变量集合相关联逻辑单元，响应于过程调用或退出而改变与当前变量集相关联的变量集合，并且改变一组变量的值，而不是与当前变量集合相关联的变量集合响应一个指令。

6. 发明申请

US20070157030A1 Cryptographic system component 审中-公开
标题翻译：密码系统组件
公开(公告)号：US20070157030A1
公开(公告)日：2007-07-05
申请号：US11323329
申请日：2005-12-30
申请人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal
发明人： Wajdi Feghali , William Hasenplaugh , Gilbert Wolrich , Daniel Cutter , Vinodh Gopal
IPC分类号： G06F12/14
CPC分类号： G06F21/602
摘要： In general, in aspect, the disclosure describes a system integrated on a single die that includes a first processor core to receive commands from at least one other processor core to perform at least one specified transformative operation on specified data, multiple processing units to perform transformative operations on data, a shared memory, and logic to transfer data between a one of the set of multiple processing units and the shared memory.
摘要翻译：一般来说，在本发明中，本公开描述了集成在单个管芯上的系统，其包括第一处理器核心，用于接收来自至少一个其他处理器核心的命令以对指定数据执行至少一个指定的变换操作，多个处理单元执行变换对数据的操作，共享存储器和用于在多个处理单元组中的一个处理单元和共享存储器之间传送数据的逻辑。

7. 发明申请

US20110106872A1 Method and apparatus for providing an area-efficient large unsigned integer multiplier 审中-公开
标题翻译：用于提供面积效率大的无符号整数乘法器的方法和装置
公开(公告)号：US20110106872A1
公开(公告)日：2011-05-05
申请号：US12157074
申请日：2008-06-06
申请人： William Hasenplaugh , Gilbert Wolrich , Vinodh Gopal , Gunnar Gaubatz , Erdinc Ozturk , Wajdi Feghali
发明人： William Hasenplaugh , Gilbert Wolrich , Vinodh Gopal , Gunnar Gaubatz , Erdinc Ozturk , Wajdi Feghali
IPC分类号： G06F7/487
CPC分类号： G06F7/5324 , G06F7/72
摘要： An area efficient multiplier having high performance at modest clock speeds is presented. The performance of the multiplier is based on optimal choice of a number of levels of Karatsuba decomposition. The multiplier may be used to perform efficient modular reduction of large numbers greater than the size of the multiplier.
摘要翻译：提出了一种在适度的时钟速度下具有高性能的区域有效乘法器。乘数的表现是基于对Karatsuba分解的多个水平的最佳选择。乘法器可用于执行大于乘数大小的大数量的有效的模块化减少。

8. 发明申请

US20080147768A1 Configurable Exponent Fifo 有权
标题翻译：可配置指数
公开(公告)号：US20080147768A1
公开(公告)日：2008-06-19
申请号：US11610841
申请日：2006-12-14
申请人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Daniel Cutter , Robert P. Ottavi
发明人： Vinodh Gopal , Wajdi Feghali , Gilbert Wolrich , Daniel Cutter , Robert P. Ottavi
IPC分类号： G06F7/38
CPC分类号： G06F7/723
摘要： The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的系统和方法。该方法包括将来自存储器的向量的第一字加载到第一寄存器中，并随后将第一个字从第一寄存器加载到第二寄存器。该方法还可以包括将第二字加载到第一寄存器中并将至少一个比特从第二寄存器加载到算术逻辑单元中。该方法还可以包括在至少一个比特上执行模幂运算以产生结果，并且至少部分地基于结果生成公开密钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

9. 发明申请

US20080148024A1 Hardware Accelerator 有权
标题翻译：硬件加速器
公开(公告)号：US20080148024A1
公开(公告)日：2008-06-19
申请号：US11610871
申请日：2006-12-14
申请人： Gilbert M. Wolrich , William Hasenplaugh , Wajdi Feghali , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Gilbert M. Wolrich , William Hasenplaugh , Wajdi Feghali , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F9/302
CPC分类号： G06F9/30014 , G06F21/72
摘要： The present disclosure provides a method for instruction processing. The method may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit. The method may further include loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand. The method may also include performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register. The method may further include loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand. The method may additionally include generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于指令处理的方法。该方法可以包括从第一寄存器，第二操作数，第二寄存器和进位输入位添加第一操作数，以产生和和执行位。该方法还可以包括将和加载到第三寄存器中，并且将进位位加载到第三寄存器的最高有效位位置以产生第三操作数。该方法还可以包括经由移位器单元在第三操作数上执行单位移位以产生移位的操作数，并将移位的操作数加载到第四寄存器中。该方法还可以包括将最小有效位加载到第四寄存器的最高有效位位置以产生第四操作数。该方法可以另外包括经由第四操作数生成第一和第二操作数的最大公约数（GCD），并且至少部分地基于GCD生成公钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

10. 发明授权

US08020142B2 Hardware accelerator 有权
标题翻译：硬件加速器
公开(公告)号：US08020142B2
公开(公告)日：2011-09-13
申请号：US11610871
申请日：2006-12-14
申请人： Gilbert M. Wolrich , William Hasenplaugh , Wajdi Feghali , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
发明人： Gilbert M. Wolrich , William Hasenplaugh , Wajdi Feghali , Daniel Cutter , Vinodh Gopal , Gunnar Gaubatz
IPC分类号： G06F9/44 , G06F9/45 , G06F7/38
CPC分类号： G06F9/30014 , G06F21/72
摘要： A method for instruction processing may include adding a first operand from a first register, a second operand from a second register and a carry input bit to generate a sum and a carry out bit, loading the sum into a third register and loading the carry out bit into a most significant bit position of the third register to generate a third operand, performing a single bit shift on the third operand via a shifter unit to produce a shifted operand and loading the shifted operand into the fourth register, loading a least significant bit from the sum into the most significant bit position of the fourth register to generate a fourth operand, generating a greatest common divisor (GCD) of the first and second operands via the fourth operand and generating a public key based on, at least in part, the GCD. Many alternatives, variations and modifications are possible.
摘要翻译：一种用于指令处理的方法可以包括从第一寄存器，第二操作数，第二寄存器和进位输入位添加第一操作数，以产生和和执行位，将所述和加载到第三寄存器并加载进位位到第三寄存器的最高有效位位置以产生第三操作数，经由移位器单元在第三操作数上执行单位移位以产生移位操作数，并将移位的操作数加载到第四寄存器中，加载最低有效位从总和到第四寄存器的最高有效位位置以产生第四操作数，经由第四操作数产生第一和第二操作数的最大公约数（GCD），并且至少部分地基于第二操作数生成公钥， GCD。许多替代方案，变化和修改是可能的。

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