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1. 发明申请

US20080159528A1 Method for Processing Multiple Operations 有权
标题翻译：多操作处理方法
公开(公告)号：US20080159528A1
公开(公告)日：2008-07-03
申请号：US11617418
申请日：2006-12-28
申请人： Wajdi Feghali , Stephanie Hirnak , Makaram Raghunandan , Yogesh Bansal , Kirk Yap , Gilbert M. Wolrich
发明人： Wajdi Feghali , Stephanie Hirnak , Makaram Raghunandan , Yogesh Bansal , Kirk Yap , Gilbert M. Wolrich
IPC分类号： H04L9/30 , H04L9/28
CPC分类号： H04L63/0485 , G06F9/30181 , G06F9/3879 , H04L63/08
摘要： In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：在一个实施例中，本公开提供了一种能够处理各种不同操作的方法。根据一个实施例的方法可以包括将配置数据从共享存储器单元加载到硬件配置寄存器中，硬件配置寄存器位于包括在硬件加速器单元内的电路内。该方法还可以包括从微引擎向具有该电路的硬件加速器单元发出命令集。该方法可以另外包括接收来自微引擎的电路处的命令集，该命令集被配置为允许处理各种不同的操作。该方法还可以包括基于加载到硬件配置寄存器中的配置数据来处理适当的操作。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

2. 发明授权

US07953221B2 Method for processing multiple operations 有权
标题翻译：处理多个操作的方法
公开(公告)号：US07953221B2
公开(公告)日：2011-05-31
申请号：US11617418
申请日：2006-12-28
申请人： Wajdi Feghali , Stephanie Hirnak , Makaram Raghunandan , Yogesh Bansal , Kirk Yap , Gilbert M. Wolrich
发明人： Wajdi Feghali , Stephanie Hirnak , Makaram Raghunandan , Yogesh Bansal , Kirk Yap , Gilbert M. Wolrich
IPC分类号： H04K1/00 , H04K1/04 , H04K1/06 , H04L9/00 , H04L9/28 , H04L9/32
CPC分类号： H04L63/0485 , G06F9/30181 , G06F9/3879 , H04L63/08
摘要： In one embodiment, the present disclosure provides a method capable of processing a variety of different operations. A method according to one embodiment may include loading configuration data from a shared memory unit into a hardware configuration register, the hardware configuration register located within circuitry included within a hardware accelerator unit. The method may also include issuing a command set from a microengine to the hardware accelerator unit having the circuitry. The method may additionally include receiving the command set at the circuitry from the microengine, the command set configured to allow for the processing of a variety of different operations. The method may further include processing an appropriate operation based upon the configuration data loaded into the hardware configuration register. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：在一个实施例中，本公开提供了一种能够处理各种不同操作的方法。根据一个实施例的方法可以包括将配置数据从共享存储器单元加载到硬件配置寄存器中，硬件配置寄存器位于包括在硬件加速器单元内的电路内。该方法还可以包括从微引擎向具有该电路的硬件加速器单元发出命令集。该方法可以另外包括接收来自微引擎的电路处的命令集，该命令集被配置为允许处理各种不同的操作。该方法还可以包括基于加载到硬件配置寄存器中的配置数据来处理适当的操作。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

3. 发明申请

US20080162806A1 Storage Accelerator 有权
标题翻译：存储加速器
公开(公告)号：US20080162806A1
公开(公告)日：2008-07-03
申请号：US11617966
申请日：2006-12-29
申请人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
发明人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
IPC分类号： G06F12/06
CPC分类号： G06F11/1076 , G06F2211/1057
摘要： The present disclosure provides a method for generating RAID syndromes. In one embodiment the method may include loading a first data byte of a first disk block and a first data byte of a second disk block from a storage device to an arithmetic logic unit. The method may further include XORing the first data byte of the first disk block and the first data byte of the second disk block to generate a first result and storing the first result in a results buffer. The method may also include iteratively repeating, loading intermediate data bytes corresponding to the first disk block and intermediate data bytes corresponding to the second disk block from the storage device to the arithmetic logic unit. The method may additionally include XORing the intermediate data bytes corresponding to the first disk block and the intermediate data bytes corresponding to the second disk block to generate intermediate results and generating a RAID syndrome based on, at least in part, the intermediate results. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于生成RAID综合征的方法。在一个实施例中，该方法可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节从存储设备加载到算术逻辑单元。该方法还可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节进行异或，以产生第一结果并将第一结果存储在结果缓冲器中。该方法还可以包括将对应于第一磁盘块的中间数据字节和对应于第二磁盘块的中间数据字节从存储设备反复重复加载到算术逻辑单元。该方法还可以包括对与第一磁盘块相对应的中间数据字节和对应于第二磁盘块的中间数据字节进行异或，以产生中间结果，并至少部分地基于中间结果生成RAID综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

4. 发明授权

US07797612B2 Storage accelerator 有权
标题翻译：存储加速器
公开(公告)号：US07797612B2
公开(公告)日：2010-09-14
申请号：US11617966
申请日：2006-12-29
申请人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
发明人： Vinodh Gopal , Yogesh Bansal , Gilbert M. Wolrich , Wajdi Feghali , Kirk Yap
IPC分类号： G11C29/00
CPC分类号： G06F11/1076 , G06F2211/1057
摘要： The present disclosure provides a method for generating RAID syndromes. In one embodiment the method may include loading a first data byte of a first disk block and a first data byte of a second disk block from a storage device to an arithmetic logic unit. The method may further include XORing the first data byte of the first disk block and the first data byte of the second disk block to generate a first result and storing the first result in a results buffer. The method may also include iteratively repeating, loading intermediate data bytes corresponding to the first disk block and intermediate data bytes corresponding to the second disk block from the storage device to the arithmetic logic unit. The method may additionally include XORing the intermediate data bytes corresponding to the first disk block and the intermediate data bytes corresponding to the second disk block to generate intermediate results and generating a RAID syndrome based on, at least in part, the intermediate results. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于生成RAID综合征的方法。在一个实施例中，该方法可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节从存储设备加载到算术逻辑单元。该方法还可以包括将第一磁盘块的第一数据字节和第二磁盘块的第一数据字节进行异或，以产生第一结果并将第一结果存储在结果缓冲器中。该方法还可以包括将对应于第一磁盘块的中间数据字节和对应于第二磁盘块的中间数据字节从存储设备反复重复加载到算术逻辑单元。该方法还可以包括对与第一磁盘块相对应的中间数据字节和对应于第二磁盘块的中间数据字节进行异或，以产生中间结果，并至少部分地基于中间结果生成RAID综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

5. 发明申请

US20090168999A1 Method and apparatus for performing cryptographic operations 有权
标题翻译：用于执行加密操作的方法和装置
公开(公告)号：US20090168999A1
公开(公告)日：2009-07-02
申请号：US12005680
申请日：2007-12-28
申请人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
发明人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
IPC分类号： H04L9/28 , H04L9/00
CPC分类号： H04L9/0631 , H04L2209/125
摘要： In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括处理器，其具有响应于第一和第二轮微操作执行一轮加密算法以在第一和第二列列上执行循环的逻辑，其中该逻辑包括半数的双数据通路加密算法宽度（或更小）的宽度。可以使用附加逻辑来组合第一和第二轮微操作的结果以获得圆形结果。描述和要求保护其他实施例。

6. 发明授权

US08189792B2 Method and apparatus for performing cryptographic operations 有权
标题翻译：用于执行加密操作的方法和装置
公开(公告)号：US08189792B2
公开(公告)日：2012-05-29
申请号：US12005680
申请日：2007-12-28
申请人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
发明人： Brent Boswell , Kirk Yap , Gilbert Wolrich , Wajdi Feghali , Vinodh Gopal , Srinivas Chennupaty , Makaram Raghunandan
IPC分类号： G06F21/00
CPC分类号： H04L9/0631 , H04L2209/125
摘要： In one embodiment, the present invention includes a processor having logic to perform a round of a cryptographic algorithm responsive to first and second round micro-operations to perform the round on first and second pairs of columns, where the logic includes dual datapaths that are half the width of the cryptographic algorithm width (or smaller). Additional logic may be used to combine the results of the first and second round micro-operations to obtain a round result. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括处理器，其具有响应于第一和第二轮微操作执行一轮加密算法以在第一和第二列列上执行循环的逻辑，其中该逻辑包括半数的双数据通路加密算法宽度（或更小）的宽度。可以使用附加逻辑来组合第一和第二轮微操作的结果以获得圆形结果。描述和要求保护其他实施例。

7. 发明授权

US08041945B2 Method and apparatus for performing an authentication after cipher operation in a network processor 有权
标题翻译：在网络处理器中进行密码操作之后进行认证的方法和装置
公开(公告)号：US08041945B2
公开(公告)日：2011-10-18
申请号：US12455038
申请日：2009-05-27
申请人： Jaroslaw J. Sydir , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
发明人： Jaroslaw J. Sydir , Kamal J. Koshy , Wajdi Feghali , Bradley A. Burres , Gilbert M. Wolrich
IPC分类号： H04L29/06
CPC分类号： H04L63/0485 , H04L9/0643 , H04L63/12 , H04L2209/125
摘要： A method and apparatus is described for processing of network data packets by a network processor having cipher processing cores and authentication processing cores which operate on data within the network data packets, in order to provide a one-pass ciphering and authentication processing of the network data packets.
摘要翻译：描述了一种方法和装置，用于通过具有对网络数据分组内的数据进行操作的密码处理核和认证处理核的网络处理器来处理网络数据分组，以便提供网络数据的一次通过加密和认证处理数据包

8. 发明授权

US07607068B2 Apparatus and method for generating a Galois-field syndrome 失效
标题翻译：用于产生伽罗瓦氏综合征的装置和方法
公开(公告)号：US07607068B2
公开(公告)日：2009-10-20
申请号：US11469222
申请日：2006-08-31
申请人： Vinodh Gopal , Gilbert M. Wolrich , Daniel Cutter , Wajdi Feghali , Robert P. Ottavi
发明人： Vinodh Gopal , Gilbert M. Wolrich , Daniel Cutter , Wajdi Feghali , Robert P. Ottavi
IPC分类号： G11C29/00
CPC分类号： G06F11/1076 , G06F2211/1054 , G06F2211/1057
摘要： The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于产生伽罗瓦域综合征的装置和方法。一个示例性方法可以包括将第一数据字节从第一存储设备加载到第一寄存器，并将第二数据字节从第二存储设备加载到第二寄存器; 将第一数据字节的最高有效位（MSB）和伽罗瓦域多项式进行比较以产生第一中间输出; 用第一数据字节的最低有效位（LSB）对第一中间输出的每个位进行异或，以产生第二中间输出; 将第二中间输出与第一数据字节的每个位进行多路复用以产生第三中间输出; 将第三中间输出的每个位与第二数据字节的每个位进行异或，以在第四中间输出处产生; 以及至少部分地基于第四中间输出产生RAID Q综合征。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

9. 发明申请

US20080148011A1 Carry/Borrow Handling 审中-公开
标题翻译：携带/借款处理
公开(公告)号：US20080148011A1
公开(公告)日：2008-06-19
申请号：US11610897
申请日：2006-12-14
申请人： Vinodh Gopal , Gilbert M. Wolrich , Gunnar Gaubatz , Daniel Cutter , Wajdi Feghali , Kaan Yuksel , Erdinc Ozturk
发明人： Vinodh Gopal , Gilbert M. Wolrich , Gunnar Gaubatz , Daniel Cutter , Wajdi Feghali , Kaan Yuksel , Erdinc Ozturk
IPC分类号： G06F9/30
CPC分类号： G06F9/3001
摘要： The present disclosure provides a system and method for performing carry/borrow handling. A method according to one embodiment may include generating a first result having a first carry or borrow from a first mathematical operation and storing the first carry or borrow and a first pointer address in a temporary register. The method may further include generating a second result having a second carry or borrow from a second mathematical operation and calling a subroutine configured to perform carry and borrow handling. The method may also include copying the first pointer address from the temporary register into a global variable. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了用于执行进位/借用处理的系统和方法。根据一个实施例的方法可以包括从第一数学运算产生具有第一进位或借位的第一结果，并将第一进位或借位以及第一指针地址存储在临时寄存器中。该方法还可以包括从第二数学运算产生具有第二进位或借位的第二结果，并调用被配置为执行进位和借位处理的子程序。该方法还可以包括将第一指针地址从临时寄存器复制到全局变量中。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

10. 发明申请

US20080144811A1 Method for Simultaneous Modular Exponentiations 有权
标题翻译：同时模块化指标的方法
公开(公告)号：US20080144811A1
公开(公告)日：2008-06-19
申请号：US11610919
申请日：2006-12-14
申请人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuskel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
发明人： Vinodh Gopal , Erdinc Ozturk , Kaan Yuskel , Gunnar Gaubatz , Wajdi Feghali , Gilbert M. Wolrich
IPC分类号： H04L9/30
CPC分类号： G06F7/723 , H04L9/302
摘要： The present disclosure provides a method for performing modular exponentiation. The method may include generating a first remainder (xp) based on an encrypted message (X) modulo a first prime number (p) and generating a second remainder (xq) based on the encrypted message (X) modulo a second prime number (q). The method may further include generating a third remainder(v1) based on the first remainder (xp) raised to a first private key number (d1) modulo the first prime number (p) and simultaneously generating a fourth remainder (v2) based on the second remainder (xq) raised to a second private key number (d2) modulo the second prime number(q). The method may also include subtracting the fourth remainder (v2) from the third remainder (v1) to yield a result (v1−v2) and multiplying the result (v1−v2) by a constant (c) to produce a second result. The method may additionally include generating a sixth remainder (h) by taking the second result modulo the first prime number (p) and multiplying the sixth remainder (h) by the second prime number (q) to produce a third result. The method may further include adding the third result and the fourth remainder (v2) to yield a final result (Y) and generating, at least in part, a public key based on the final result (Y). Of course, many alternatives, variations and modifications are possible without departing from this embodiment.
摘要翻译：本公开提供了一种用于执行模幂运算的方法。该方法可以包括基于第一素数（p）模数的加密消息（X）生成第一余数（xp），并且基于加密消息（X）生成第二余数（xq），第二素数（q））。该方法还可以包括：基于第一余数（xp）产生第三余数（v1），所述第一余数（xp）基于所述第一余数（xp）生成第一素数（p）的第一私钥数（d1）并同时生成第四余数第二余数（xq）升至第二素数（q）的第二私钥号（d2）。该方法还可以包括从第三余数（v1）中减去第四余数（v2）以产生结果（v1-v2）并将结果（v1-v2）乘以常数（c）以产生第二结果。该方法可以另外包括通过将第二结果以第一素数（p）取模并将第六余数（h）乘以第二素数（q）产生第三结果来产生第六余数（h）。该方法还可以包括添加第三结果和第四余数（v2）以产生最终结果（Y），并且至少部分地基于最终结果（Y）生成公钥。当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

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