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1. 发明申请

US20120112302A1 Novel Integration Process to Improve Focus Leveling Within a Lot Process Variation 有权
标题翻译：新的集成过程，以提高在一个批次过程变化中的焦点调平
公开(公告)号：US20120112302A1
公开(公告)日：2012-05-10
申请号：US12941375
申请日：2010-11-08
申请人： Wai-Kin Li , Wu-Song Huang , Dario Leonardo Goldfarb , Martin Glodde , Edward Engbrecht , Yiheng Xu
发明人： Wai-Kin Li , Wu-Song Huang , Dario Leonardo Goldfarb , Martin Glodde , Edward Engbrecht , Yiheng Xu
IPC分类号： H01L31/0232
CPC分类号： H01L21/0332 , G03F7/091 , G03F7/094 , G03F9/7026
摘要： A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer.
摘要翻译：描述了改善半导体晶片的聚焦调平响应的方法。该方法包括在半导体衬底上组合有机和无机或金属近红外（NIR）硬掩模; 在组合的有机NIR吸收和无机或金属NIR吸收硬掩模上形成抗反射涂层（ARC）层; 以及在所述ARC层上形成光致抗蚀剂层。还描述了半导体结构，其包括基板，位于结构上方的抗蚀剂层; 以及位于衬底上方的吸收层。吸收层包括无机或金属NIR吸收硬掩模层。

2. 发明授权

US08395228B2 Integration process to improve focus leveling within a lot process variation 有权
标题翻译：整合过程可以在很多过程变化中提高焦点调平
公开(公告)号：US08395228B2
公开(公告)日：2013-03-12
申请号：US12941375
申请日：2010-11-08
申请人： Wai-Kin Li , Wu-Song Huang , Dario Leonardo Goldfarb , Martin Glodde , Edward Engbrecht , Yiheng Xu
发明人： Wai-Kin Li , Wu-Song Huang , Dario Leonardo Goldfarb , Martin Glodde , Edward Engbrecht , Yiheng Xu
IPC分类号： H01L21/02
CPC分类号： H01L21/0332 , G03F7/091 , G03F7/094 , G03F9/7026
摘要： A method of improving the focus leveling response of a semiconductor wafer is described. The method includes combining organic and inorganic or metallic near infrared (NIR) hardmask on a semiconductor substrate; forming an anti-reflective coating (ARC) layer on the combined organic NIR-absorption and the inorganic or metallic NIR-absorption hardmask; and forming a photoresist layer on the ARC layer. A semiconductor structure is also described including a substrate, a resist layer located over the structure; and an absorptive layer located over the substrate. The absorptive layer includes an inorganic or metallic NIR-absorbing hardmask layer.
摘要翻译：描述了改善半导体晶片的聚焦调平响应的方法。该方法包括在半导体衬底上组合有机和无机或金属近红外（NIR）硬掩模; 在组合的有机NIR吸收和无机或金属NIR吸收硬掩模上形成抗反射涂层（ARC）层; 以及在所述ARC层上形成光致抗蚀剂层。还描述了半导体结构，其包括基板，位于结构上方的抗蚀剂层; 以及位于衬底上方的吸收层。吸收层包括无机或金属NIR吸收硬掩模层。

3. 发明授权

US08685850B2 System and method of plating conductive gate contacts on metal gates for self-aligned contact interconnections 有权
标题翻译：在金属栅极上镀覆导电栅极触点的自对准触点互连的系统和方法
公开(公告)号：US08685850B2
公开(公告)日：2014-04-01
申请号：US13494973
申请日：2012-06-12
申请人： John H. Zhang , Lawrence A. Clevenger , Carl J. Radens , Yiheng Xu
发明人： John H. Zhang , Lawrence A. Clevenger , Carl J. Radens , Yiheng Xu
IPC分类号： H01L21/3205 , H01L21/335
CPC分类号： H01L29/7834 , H01L21/28518 , H01L21/28562 , H01L21/288 , H01L21/2885 , H01L21/31116 , H01L21/76816 , H01L21/76819 , H01L21/76834 , H01L21/7684 , H01L21/76885 , H01L21/76897 , H01L21/823842 , H01L21/823871 , H01L29/1054 , H01L29/165 , H01L29/41783 , H01L29/495 , H01L29/665 , H01L29/6659
摘要： According to one embodiment of the invention, the gate contact is formed by a selective deposition on the gate electrode. One acceptable technique for the selective deposition is by plating. Plating is one process by which a metal structure, such as a gate contact, may be formed directly on the gate electrode. The plating is carried out by immersing the semiconductor die in a plating solution with the gate electrode exposed. The gate contact is plated onto the gate electrode and thus is ensured of being fully aligned exactly to the gate electrode. After this, the appropriate dielectric layers are formed adjacent the gate contact and over the source and drain to ensure that the gate electrode is electrically isolated from other components of the transistor.
摘要翻译：根据本发明的一个实施例，通过在栅电极上的选择性沉积形成栅极接触。用于选择性沉积的一种可接受的技术是通过电镀。电镀是可以直接在栅电极上形成诸如栅极接触的金属结构的一个过程。通过将半导体管芯浸渍在露出电极的电镀液中来进行电镀。栅极接触电镀在栅电极上，因此确保与栅电极完全对准。之后，在栅极接触点和源极和漏极之间形成适当的电介质层，以确保栅电极与晶体管的其它部件电隔离。

4. 发明授权

US08680577B2 Recessed gate field effect transistor 有权
标题翻译：嵌入式栅极场效应晶体管
公开(公告)号：US08680577B2
公开(公告)日：2014-03-25
申请号：US13494965
申请日：2012-06-12
申请人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu
发明人： John H. Zhang , Lawrence A. Clevenger , Carl Radens , Yiheng Xu
IPC分类号： H01L29/78
CPC分类号： H01L29/66666 , H01L21/28008 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/7781
摘要： A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.
摘要翻译：一种半导体器件，其具有位于源极区域和漏极区域之间的与栅极电极的两侧相邻的凹部中的栅极。沟道区域低于源极区域的大部分以及漏极区域和整个栅极电极的大部分。

5. 发明申请

US20120187530A1 USING BACKSIDE PASSIVE ELEMENTS FOR MULTILEVEL 3D WAFERS ALIGNMENT APPLICATIONS 有权
标题翻译：使用背面被动元素进行多级3D WAFERS对齐应用
公开(公告)号：US20120187530A1
公开(公告)日：2012-07-26
申请号：US13324791
申请日：2011-12-13
申请人： John H. Zhang , Lawrence A. Clevenger , Yiheng Xu
发明人： John H. Zhang , Lawrence A. Clevenger , Yiheng Xu
IPC分类号： H01L27/06 , H01L21/66
CPC分类号： H01L27/0694 , H01L21/76898 , H01L23/481 , H01L23/5227 , H01L23/645 , H01L24/05 , H01L24/13 , H01L24/29 , H01L24/32 , H01L24/80 , H01L24/94 , H01L25/0657 , H01L25/50 , H01L2223/6677 , H01L2224/02372 , H01L2224/0401 , H01L2224/05547 , H01L2224/05548 , H01L2224/13024 , H01L2224/131 , H01L2224/2919 , H01L2224/32145 , H01L2224/80357 , H01L2224/80805 , H01L2224/80895 , H01L2224/80896 , H01L2225/06541 , H01L2924/01029 , H01L2924/01322 , H01L2924/14 , H01L2924/1461 , H01L2924/181 , H01L2924/19015 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19104 , H01L2924/014 , H01L2924/00
摘要： Passive circuit elements are formed at surfaces of two integrated circuit wafers. The passive circuit elements are utilized to align the two integrated circuit wafers to form an integrated circuit wafer stack.
摘要翻译：无源电路元件形成在两个集成电路晶片的表面。无源电路元件用于对准两个集成电路晶片以形成集成电路晶片叠层。

6. 发明授权

US07570174B2 Real time alarm classification and method of use 失效
标题翻译：实时报警分类及使用方法
公开(公告)号：US07570174B2
公开(公告)日：2009-08-04
申请号：US11693162
申请日：2007-03-29
申请人： Joseph Byrne , Harry D. Clark , Gary R. Moore , Michael L. Passow , Yiheng Xu
发明人： Joseph Byrne , Harry D. Clark , Gary R. Moore , Michael L. Passow , Yiheng Xu
IPC分类号： G08B17/10
CPC分类号： G05B23/0281
摘要： A real time alarm classification system and method of use and, more particularly, to a residual gas analyzer configured to identify specific root causes of an abnormal condition such as, for example, contamination, undesirable process variability and equipment malfunction in wafer processing. The real-time alarm classification system comprises a computer infrastructure operable to: generate top contributors associated with an alarm triggered by sensed abnormal conditions; compare the top contributors to contributors of historic RGA (residual gas analyzer) alarms of known root causes that were generated by a validated model; and provide a probable root cause of the sensed abnormal conditions when a match is found between the top contributors and the contributors associated with the historic RGA alarms of known root causes. A method and computer readable medium is also contemplated to provide the processes.
摘要翻译：更具体地说，涉及一种残留气体分析器，该残留气体分析器被配置为识别晶片处理中诸如污染，不期望的过程变化性和设备故障等异常状况的特定根本原因。所述实时报警分类系统包括：计算机基础设施，其可操作地：产生与由感测到的异常状况触发的报警相关联的最高贡献者; 比较由经验证的模型生成的已知根本原因的历史RGA（残留气体分析仪）报警的贡献者的主要贡献者; 并且当在顶级贡献者和与已知根本原因的历史RGA警报相关联的贡献者之间找到匹配时，提供感测到的异常状况的可能的根本原因。还考虑了一种方法和计算机可读介质来提供这些过程。

7. 发明申请

US20120313144A1 RECESSED GATE FIELD EFFECT TRANSISTOR 有权
标题翻译：闭门控场效应晶体管
公开(公告)号：US20120313144A1
公开(公告)日：2012-12-13
申请号：US13494965
申请日：2012-06-12
申请人： John H. ZHANG , Lawrence A. Clevenger , Carl Radens , Yiheng Xu
发明人： John H. ZHANG , Lawrence A. Clevenger , Carl Radens , Yiheng Xu
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66666 , H01L21/28008 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/7781
摘要： A semiconductor device having a gate positioned in a recess between the source region and a drain region that are adjacent either side of the gate electrode. A channel region is below a majority of the source region as well as a majority of the drain region and the entire gate electrode.
摘要翻译：一种半导体器件，其具有位于源极区域和漏极区域之间的与栅极电极的两侧相邻的凹部中的栅极。沟道区域低于源极区域的大部分以及漏极区域和整个栅极电极的大部分。

8. 发明授权

US08026166B2 Interconnect structures comprising capping layers with low dielectric constants and methods of making the same 失效
标题翻译：互连结构包括具有低介电常数的封端层及其制造方法
公开(公告)号：US08026166B2
公开(公告)日：2011-09-27
申请号：US12190131
申请日：2008-08-12
申请人： Griselda Bonilla , Tien Cheng , Lawrence A. Clevenger , Stephan Grunow , Chao-Kun Hu , Roger A. Quon , Zhiguo Sun , Wei-tsui Tseng , Yiheng Xu , Yun Wang , Hyeok-sang Oh
发明人： Griselda Bonilla , Tien Cheng , Lawrence A. Clevenger , Stephan Grunow , Chao-Kun Hu , Roger A. Quon , Zhiguo Sun , Wei-tsui Tseng , Yiheng Xu , Yun Wang , Hyeok-sang Oh
IPC分类号： H01L21/4763
CPC分类号： H01L21/76834 , H01L21/76826 , H01L21/76832 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.
摘要翻译：提供包括具有低介电常数和良好氧阻隔性能的封盖层的互连结构及其制备方法。在一个实施例中，集成电路结构包括：设置在半导体衬底之上的层间电介质层; 嵌入在所述层间电介质层中的导电互连; 包括设置在所述导电互连上的SiwCxNyHz的第一覆盖层; 包含设置在第一覆盖层上的介电常数小于约4的SiaCbNcHd（具有较小的N）的第二覆盖层; 以及第三覆盖层，其包括设置在所述第二覆盖层上的SiwCxNyHz，其中a + b + c + d = 1.0和a，b，c和d各自大于0且小于1，并且其中w + x + y + z = 1.0，w，x，y和z分别大于0且小于1。

9. 发明申请

US20100038793A1 INTERCONNECT STRUCTURES COMPRISING CAPPING LAYERS WITH LOW DIELECTRIC CONSTANTS AND METHODS OF MAKING THE SAME 失效
标题翻译：包含具有低介电常数的封装层的互连结构及其制造方法
公开(公告)号：US20100038793A1
公开(公告)日：2010-02-18
申请号：US12190131
申请日：2008-08-12
申请人： Griselda Bonilla , Tien Cheng , Lawrence A. Clevenger , Stephan Grunow , Chao-Kun Hu , Roger A. Quon , Zhiguo Sun , Wei-tsui Tseng , Yiheng Xu , Yun Wang , Hyeok-Sang Oh
发明人： Griselda Bonilla , Tien Cheng , Lawrence A. Clevenger , Stephan Grunow , Chao-Kun Hu , Roger A. Quon , Zhiguo Sun , Wei-tsui Tseng , Yiheng Xu , Yun Wang , Hyeok-Sang Oh
IPC分类号： H01L23/48
CPC分类号： H01L21/76834 , H01L21/76826 , H01L21/76832 , H01L21/76835 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed above a semiconductor substrate; a conductive interconnect embedded in the interlevel dielectric layer; a first capping layer comprising SiwCxNyHz disposed upon the conductive interconnect; a second capping layer comprising SiaCbNcHd (has less N) having a dielectric constant less than about 4 disposed upon the first capping layer; and a third capping layer comprising SiwCxNyHz disposed upon the second capping layer, wherein a+b+c+d=1.0 and a, b, c, and d are each greater than 0 and less than 1, and wherein w+x+y+z=1.0 and w, x, y, and z are each greater than 0 and less than 1.
摘要翻译：提供包括具有低介电常数和良好氧阻隔性能的封盖层的互连结构及其制备方法。在一个实施例中，集成电路结构包括：设置在半导体衬底之上的层间电介质层; 嵌入在所述层间电介质层中的导电互连; 包括设置在所述导电互连上的SiwCxNyHz的第一覆盖层; 包含设置在第一覆盖层上的介电常数小于约4的SiaCbNcHd（具有较小N）的第二覆盖层; 以及第三覆盖层，其包括设置在所述第二覆盖层上的SiwCxNyHz，其中a + b + c + d = 1.0和a，b，c和d各自大于0且小于1，并且其中w + x + y + z = 1.0，w，x，y和z分别大于0且小于1。

10. 发明授权

US08623673B1 Structure and method for detecting defects in BEOL processing 失效
标题翻译：用于检测BEOL处理缺陷的结构和方法
公开(公告)号：US08623673B1
公开(公告)日：2014-01-07
申请号：US13572720
申请日：2012-08-13
申请人： Thomas W. Dyer , Tze-Man Ko , Yiheng Xu , Shaoning Yao
发明人： Thomas W. Dyer , Tze-Man Ko , Yiheng Xu , Shaoning Yao
IPC分类号： H01L21/66 , H01L21/306
CPC分类号： H01L22/34 , H01L22/30
摘要： A test structure and method for monitoring process uniformity. Embodiments of the invention include test structures having a first metallization layer, a second metallization layer formed above the first metallization layer, a defect-generating region in a first metallization layer, a defect-dispersing region in the second metallization layer above the defect-generating region; and a defect-detecting region in the second metallization layer adjacent to the defect-dispersing region. The defect-generating region of the exemplary embodiment may have zero pattern density, uniform non-zero pattern density, or non-uniform non-zero pattern density. The defect-detecting region may include a test pattern such as, a comb-serpentine structure. Embodiments may include more than one defect-generating region, more than one defect-dispersing region, or more than one defect-detecting region. Embodiments may further include methods of manufacturing said test structures and methods of utilizing said test structures to monitor back end processes and determine if such processes are within specification limits.
摘要翻译：一种用于监测过程均匀性的测试结构和方法。本发明的实施例包括具有第一金属化层的第一金属化层，在第一金属化层上形成的第二金属化层，第一金属化层中的缺陷产生区，在产生缺陷的第二金属化层中的缺陷分散区的测试结构地区; 以及与所述缺陷分散区域相邻的所述第二金属化层中的缺陷检测区域。示例性实施例的缺陷产生区域可以具有零图案密度，均匀的非零图案密度或非均匀非零图案密度。缺陷检测区域可以包括诸如梳状蛇形结构的测试图案。实施例可以包括多于一个缺陷产生区域，多于一个缺陷分散区域或多于一个缺陷检测区域。实施例还可以包括制造所述测试结构的方法以及利用所述测试结构来监测后端处理并确定这些过程是否在规定范围内的方法。

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