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    • 1. 发明授权
    • On-chip R-C time constant calibration
    • 片上R-C时间常数校准
    • US07548129B2
    • 2009-06-16
    • US11552139
    • 2006-10-23
    • Wai LauChao-Wen TsengWei-Chien ChiuYing-Chi Chen
    • Wai LauChao-Wen TsengWei-Chien ChiuYing-Chi Chen
    • H03K3/02H04B1/10
    • H03H11/1291H03H7/0153H03H2210/043H03K3/0231H03K3/02337
    • An integrated tuner includes circuitry to receive a television signal, a quadrature mixer coupled to the output of the circuitry, a polyphase filter coupled to the output of the quadrature mixer, a relaxation oscillator, and a digital calibration module. The relaxation oscillator generates a clock having a period that is directly proportional to the on-chip RC time constant. The clock is fed into a counter of the digital calibration module. The counter is started and stopped at predefined time intervals by a finite state machine. The finite state machine updates the calibration code based on a successive approximation algorithm according to the end count results received from the counter. The digital calibration module outputs the updated calibration code to the polyphase filter and to the relaxation oscillator.
    • 集成调谐器包括接收电视信号的电路,耦合到电路的输出的正交混频器,耦合到正交混频器的输出的多相滤波器,张弛振荡器和数字校准模块。 张弛振荡器产生具有与片上RC时间常数成正比的周期的时钟。 时钟被馈送到数字校准模块的计数器。 计数器由有限状态机以预定义的时间间隔启动和停止。 有限状态机根据从计数器接收的结束计数结果,基于逐次逼近算法来更新校准码。 数字校准模块将更新的校准代码输出到多相滤波器和张弛振荡器。
    • 2. 发明申请
    • On-chip R-C time constant calibration
    • 片上R-C时间常数校准
    • US20070109063A1
    • 2007-05-17
    • US11552139
    • 2006-10-23
    • Wai LauChao-Wen TsengWei-Chien ChiuYing-Chi Chen
    • Wai LauChao-Wen TsengWei-Chien ChiuYing-Chi Chen
    • H03K3/26
    • H03H11/1291H03H7/0153H03H2210/043H03K3/0231H03K3/02337
    • An integrated tuner includes circuitry to receive a television signal, a quadrature mixer coupled to the output of the circuitry, a polyphase filter coupled to the output of the quadrature mixer, a relaxation oscillator, and a digital calibration module. The relaxation oscillator generates a clock having a period that is directly proportional to the on-chip RC time constant. The clock is fed into a counter of the digital calibration module. The counter is started and stopped at predefined time intervals by a finite state machine. The finite state machine updates the calibration code based on a successive approximation algorithm according to the end count results received from the counter. The digital calibration module outputs the updated calibration code to the polyphase filter and to the relaxation oscillator.
    • 集成调谐器包括接收电视信号的电路,耦合到电路的输出的正交混频器,耦合到正交混频器的输出的多相滤波器,张弛振荡器和数字校准模块。 张弛振荡器产生具有与片上RC时间常数成正比的周期的时钟。 时钟被馈送到数字校准模块的计数器。 计数器由有限状态机以预定义的时间间隔启动和停止。 有限状态机根据从计数器接收的结束计数结果,基于逐次逼近算法来更新校准码。 数字校准模块将更新的校准代码输出到多相滤波器和张弛振荡器。